From b44ef95a9a71d3012951eea91d6daf2c36e5a1e1 Mon Sep 17 00:00:00 2001 From: Kamyar Mohajerani Date: Fri, 27 Sep 2024 18:28:52 -0400 Subject: [PATCH] [VivadoSim] more robust quoting --- src/xeda/flows/vivado/templates/vivado_sim.tcl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/xeda/flows/vivado/templates/vivado_sim.tcl b/src/xeda/flows/vivado/templates/vivado_sim.tcl index ef4d01c..f85be56 100644 --- a/src/xeda/flows/vivado/templates/vivado_sim.tcl +++ b/src/xeda/flows/vivado/templates/vivado_sim.tcl @@ -19,17 +19,17 @@ puts "\n===========================( Analyzing HDL Sources )==================== {%- for src in design.sim_sources %} {%- if src.type.name == "Verilog" %} puts "Analyzing Verilog file {{src.file}}" -if { [catch {eval exec xvlog ${analyze_flags} \"{{src.file}}\" } error]} { +if { [catch {eval exec xvlog ${analyze_flags} {" {{- src.file -}} "} } error]} { errorExit $error } {%- elif src.type.name == "SystemVerilog" %} puts "Analyzing SystemVerilog file {{src.file}}" -if { [catch {eval exec xvlog ${analyze_flags} -sv \"{{src.file}}\" } error]} { +if { [catch {eval exec xvlog ${analyze_flags} -sv {" {{- src.file -}} "} } error]} { errorExit $error } {%- elif src.type.name == "Vhdl" %} -puts "Analyzing VHDL file {{src.file}} {% if design.language.vhdl.standard -%} [VHDL {{design.language.vhdl.standard}}]" {%- endif %} -if { [catch {eval exec xvhdl ${analyze_flags} {% if design.language.vhdl.standard == "08" %} -2008 {% elif design.language.vhdl.standard == "93" %} -93_mode {% endif %} \"{{src.file}}\" } error]} { +puts "Analyzing VHDL file {{src.file}} {% if design.language.vhdl.standard -%} [VHDL {{design.language.vhdl.standard}}] {%- endif %}" +if { [catch {eval exec xvhdl ${analyze_flags} {% if design.language.vhdl.standard == "08" %} -2008 {% elif design.language.vhdl.standard == "93" %} -93_mode {% endif %} {" {{- src.file -}} "} } error]} { errorExit $error } {%- endif %}