From 148ddba3736ac478f22f55f053ea260451e2c7da Mon Sep 17 00:00:00 2001
From: Kamyar Mohajerani <kammoh@gmail.com>
Date: Sat, 8 Jun 2024 23:54:48 -0400
Subject: [PATCH] fix design clock validation

---
 src/xeda/design.py | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/xeda/design.py b/src/xeda/design.py
index 8f9dabe..f68a6b8 100644
--- a/src/xeda/design.py
+++ b/src/xeda/design.py
@@ -419,16 +419,24 @@ def rtl_settings_validate(cls, values):  # pylint: disable=no-self-argument
         clock_port = values.get("clock_port")
         clocks = values.get("clocks")
 
+        def conv_clock(clock):
+            if isinstance(clock, dict):
+                clock = Clock(**clock)
+            elif isinstance(clock, str):
+                clock = Clock(port=clock_port)
+            return clock
+
         if clocks is None:
             clocks = {}
+        elif isinstance(clocks, list):
+            clocks = {clk.name or clk.port: clk for clk in map(conv_clock, clocks) if clk}
         if not clock:
             if clock_port:
                 clock = Clock(port=clock_port)
             elif len(clocks) == 1:
                 clock = list(clocks.values())[0]
         if clock:
-            if isinstance(clock, dict):
-                clock = Clock(**clock)
+            clock = conv_clock(clock)
             if not clock_port:
                 clock_port = clock.port
             if not clocks: