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README
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####################################################################################
Copyright (c) 2014, University of British Columbia (UBC) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the University of British Columbia (UBC) nor the names
of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
####################################################################################
####################################################################################
Modular Multi-ported SRAM-based Memories; University of British Columbia, 2014
Author: Ameer M. Abdelhadi ([email protected], [email protected])
A fully parameterized and generic Verilog implementation of the suggested
modular multi-ported SRAM-based memories, together with previous approaches
are provided as open source hardware. A run-in-batch flow manager to simulate
and synthesize various designs with various parameters in batch using Altera's
ModelSim and Quartus II is also provided.
Please refer to the full paper for more information:
A. Abdelhadi and G. G.F. Lemieux, "Modular Multi-ported SRAM-based Memories,"
ACM/SIGDA Intl Symp. on Field-Programmable. Gate Arrays (FPGA 14), Feb. 2014.
http://www.ece.ubc.ca/~lemieux/publications/abdelhadi-fpga2014.pdf
LICENSE: BSD 3-Clause ("BSD New" or "BSD Simplified") license.
####################################################################################
####################################################################################
Files and directories in this package:
======================================
- README : This file
- LICENSE : BSD 3-Clause ("BSD New" or "BSD Simplified") license
- fpga14-paper.pdf : ACM/SIGDA Intl Symp. on Field-Programmable. Gate Arrays (FPGA'14) paper
- fpga14-slides.pdf: ACM/SIGDA Intl Symp. on Field-Programmable. Gate Arrays (FPGA'14) slides
- sim : A C-shell script: A run-in-batch simulation flow manager
- syn : A C-shell script: A run-in-batch synthesis flow manager
- config.vh : Verilog: Generated by syn script, contains design parameters
- utils.vh : Verilog: Design pre-compile utilities
- mrram.v : Verilog: Multiread-RAM using bank replication; based on generic
dual-ported RAM; optional 1 or 2-stage bypass
- dpram.v : Verilog: Generic dual-ported RAM/ optional 1 or 2-stage bypass
- mpram_gen.v : Verilog: Generic multiported-RAM; Old data will be read in case of RAW
- mpram_reg.v : Verilog: Generic register-based multiported-RAM
- mpram_xor.v : Verilog: Multiported-RAM based on XOR implementation
- lvt_reg.v : Verilog: Register-based binary-coded LVT (Live-Value-Table)
- lvt_bin.v : Verilog: Binary-coded LVT (Live-Value-Table)
- lvt_1ht.v : Verilog: Onehot-coded LVT (Live-Value-Table)
- mpram_lvt_reg.v : Verilog: Multiported-RAM based on register-based LVT
- mpram_lvt_bin.v : Verilog: Multiported-RAM based on binary-coded LVT
- mpram_lvt_1ht.v : Verilog: Multiported-RAM based on onehot-coded LVT
- mpram.v : Verilog: Multiported-RAM: top hierarchy
- mpram_tb.v : Verilog: Multiported-RAM testbench
- mpram_wrp.v : Verilog: Multiported-RAM synthesis wrapper
- mpram.qpf : Quartus II Project File
- mpram.qsf : Quartus II Settings File
- syn.res : A list of synthesis results, each run in a separate line, including:
frequency, resources usage, and runtime
- syn.res.example : Example results for 628 different designs
- sim.res : A list of simulation results, each run in a separate line,
including all design styles
- log/ : Altera's logs and reports
####################################################################################
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Multi-ported RAM module instantiation:
=======================================
All *.v & *.vh files in this package should be copied into your work directory.
Copy the following instantiation, change parameters and connectivity to fit your
design.
// instantiate a multiported-RAM
mpram #( .MEMD (MEMD ), // positive integer: memory depth
.DATAW (DATAW ), // positive integer: data width
.nRPORTS(nRPORTS), // positive integer: number of reading ports
.nWPORTS(nWPORTS), // positive integer: number of writing ports
.TYPE (TYPE ), // text: multi-port RAM implementation type:
// "AUTO" : Choose automatically
// "REG" : Register-based
// "XOR" : XOR-based
// "LVTREG": Register-based LVT
// "LVTBIN": Binary-coded I-LVT-based
// "LVT1HT": Onehot-coded I-LVT-based
.BYP (BYP ), // text: Bypassing type:
// WAW: Allow Write-After-Write
// (need to bypass feedback ram)
// RAW: New data for Read-after-Write
// (need to bypass output ram)
// RDW: New data for Read-During-Write
.IFILE ("" )) // text: initializtion file, optional
mpram_inst ( .clk (clk ), // clock
.WEnb (WEnb ), // write enable for each writing port
// - input : [nWPORTS-1:0 ]
.WAddr(WAddr), // write addresses - packed from nWPORTS write ports
// - input : [`log2(MEMD)*nWPORTS-1:0]
.WData(WData), // write data - packed from nRPORTS read ports
// - output: [DATAW *nWPORTS-1:0]
.RAddr(RAddr), // read addresses - packed from nRPORTS read ports
// - input : [`log2(MEMD)*nRPORTS-1:0]
.RData(RData)); // read data - packed from nRPORTS read ports
// - output: [DATAW *nRPORTS-1:0]
####################################################################################
####################################################################################
sim: A run-in-batch flow manager for simulation
===============================================
USAGE:
./sim <Depth List> <Width List> <#WritePorts List> <#ReadPorts List> <#Cycles>
-Use a comma delimited list; no spaces; can be surrounded by brackets ()[]{}<>
-RAM depth, width, number of read/write ports and cycles are positive integers
EXAMPLES:
./sim 1024 32 3 2 1000000
Simulate 1M cycles of a 1K lines RAM, 32 bits width, 3 write & 2 read ports
./sim 512,1024 8,16,32 2,3,4 1,2,3,4 1000000
Simulate 1M cycles of RAMs with 512 or 1024 lines, 8, 16, or 32 bits width,
2,3, or 4 write ports, 1,2,3, or 4 read ports. Total of 72 RAM combinations
The following files and directories will be created after simulation :
- sim.res : A list of simulation results, each run in a separate line,
including all design styles.
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syn: A run-in-batch flow manager for synthesis
==============================================
USAGE:
./syn <Architecture List> <Bypass List> <Depth List> <Width List> \
<#Write Ports List> <#Read Ports List>
-Use a comma delimited list; no spaces; can be surrounded by brackets ()[]{}<>
-RAM depth, width, number of read/write ports and cycles are positive integers
-Architecture is one of: REG, XOR, LVTREG, LVTBIN, or LVT1HT
- REG : Register-based multi-ported RAM
- XOR : XOR-based multi-ported RAM
- LVTREG: Register-based LVT multi-ported RAM
- LVTBIN: Binary-coded I-LVT-based multi-ported RAM
- LVT1HT: Onehot-coded I-LVT-based multi-ported RAM
-Bypass list is one of: NON, WAW, RAW, or RDW
- WAW: Allow Write-After-Write (need to bypass feedback RAM)
- RAW: new data for Read-after-Write (need to bypass output RAM)
- RDW: new data for Read-During-Write
EXAMPLES:
./syn XOR NON 1024 32 3 2
Synthesis a XOR-based RAM with no bypassing; 1K lines RAM; 32 bits width;
3 write & 2 read ports
./syn LVTBIN,LVT1HT RAW,RDW 512,1024 8,16,32 2,3,4 1,2,3,4
Synthesis LVTBIN and LVT1HT RAMs with new data RAW and RDW bypassing; 512
and 1024 lines; 8,16, and 32 data width; 2,3, and 4 write ports; 1,2,3, and
4 read ports. Total of 144 RAM combinations.
The following files and directories will be created after compilation:
- syn.res : A list of results, each run in a separate line, including:
frequency, resources usage, and runtime
- log/ : Altera's logs and reports
####################################################################################