From c5ebffb99178ba275916599209e0dc748c59f23f Mon Sep 17 00:00:00 2001 From: Justin Chang <13309614+jychang48@users.noreply.github.com> Date: Thu, 29 Aug 2024 13:27:36 -0400 Subject: [PATCH] Seismic stencil codes - three part blog series --------- Co-authored-by: Ossian O'Reilly Co-authored-by: Saad Rahim (AMD) <44449863+saadrahim@users.noreply.github.com> --- .../seismic-stencils/figures/aligned_x.png | Bin 0 -> 27462 bytes .../seismic-stencils/figures/aligned_y.png | Bin 0 -> 48147 bytes .../seismic-stencils/figures/alignment.png | Bin 0 -> 26910 bytes .../figures/sliding_window.png | Bin 0 -> 45807 bytes .../figures/sliding_window_1.svg | 784 ++++++++++ .../figures/sliding_window_2.svg | 804 ++++++++++ .../figures/sliding_window_3.svg | 744 ++++++++++ .../figures/sliding_window_4.svg | 816 +++++++++++ .../figures/sliding_window_overview.png | Bin 0 -> 34364 bytes .../figures/sliding_window_xyz.png | Bin 0 -> 49390 bytes .../seismic-stencils/figures/unaligned_x.png | Bin 0 -> 29063 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+ 81 + 100 + 121 + 144 + 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + Output array + Sliding window + Load the first 2*R elements + + diff --git a/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_2.svg b/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_2.svg new file mode 100644 index 0000000..44e0c5a --- /dev/null +++ b/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_2.svg @@ -0,0 +1,804 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + Input array + + + + + + + + + + + + + + + + 1 + 4 + 9 + 16 + + + + + + + + + + + + + + + + 25 + 36 + 49 + 64 + 81 + 100 + 121 + 144 + 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + Output array + Sliding window + Load next element + + + 81 + 2 + Compute finite difference & store output + + diff --git a/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_3.svg b/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_3.svg new file mode 100644 index 0000000..e465f4e --- /dev/null +++ b/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_3.svg @@ -0,0 +1,744 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + 1 + 4 + 9 + 16 + 25 + 36 + 49 + 64 + Old sliding window + + 81 + + + + + + + + + 4 + 9 + 16 + 25 + 36 + 49 + 64 + New sliding window + + 81 + 81 + + + + + + + + + shift values forward + + diff --git a/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_4.svg b/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_4.svg new file mode 100644 index 0000000..3bfcd5d --- /dev/null +++ b/blogs/high-performance-computing/seismic-stencils/figures/sliding_window_4.svg @@ -0,0 +1,816 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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Scientific Computing +category: Applications & models +language: English +myst: + html_meta: + "description lang=en": "Seismic Stencil Codes - Part 1" + "keywords": "HPC, finite difference, Seismic, PDE, MI250, performance" + "property=og:locale": "en_US" +--- + +# Seismic stencil codes - part 1 + +12 Aug, 2024 by {hoverxref}`Justin Chang` and {hoverxref}`Ossian O'Reilly`. + +Seismic workloads in the HPC space have a long history of being powered +by high-order finite difference methods on structured grids. This trend +continues to this day. While there is a rich body of work of +optimization techniques and strategies, there is currently no known +\"one size fits all\"-approach that works across the broad spectrum of +physical models. Many tradeoffs impact the overall +performance of propagation algorithms that depend mainly on discretization, and hardware +characteristics. GPU acceleration provides a cost-effective way to +meet the massive demand for processing the evergrowing seismic data volumes. +A distinguishing feature of seismic workloads compared to +other stencil-based areas e.g., climate and weather modeling +is the prevalent use of high-order targeting for better accuracy. In the seismic exploration +space, high-order finite differencing is the de facto standard method +because it offers a favorable trade-off between numerical accuracy and +computational efficiency. High-order stencils are characterized by a +wider or larger stencil radius. Like many stencil patterns, the stencils +in seismic codes tend to be memory or bandwidth-bound. As the +stencil radius increases, the higher the arithmetic intensity +(floating-point instructions/memory load-store instructions) becomes +provided one can achieve a high degree of data reuse. As a result, high-order stencil codes have a tendency to put a significant amount of +pressure on the memory subsystem. While there is no \"one size fits +all\" approach, a few techniques form the basic building +blocks found in most implementations across the vast landscape of +seismic models. In this blog post and upcoming posts, we will explain +and demonstrate how some of these techniques can be implemented on AMD +Instinct accelerators and leveraged for getting the most out of the +hardware\'s performance for accelerating seismic stencil codes. + +## Isotropic acoustic wave equation + +Seismic stencil codes are mainly concerned with discretizing different +types of wave equations. These wave equation solvers form the +fundamental building blocks of reverse time migration (RTM) and full +waveform inversion (FWI) solvers; designed to image the Earth\'s +subsurface structure for oil and gas exploration. The governing +equations range from solving the acoustic wave equation to the elastic wave +equation in various types of media. Arguably the most well-studied +equation is the isotropic and constant density acoustic wave equation in +second form. This equation is solved for the pressure field $p(x,y,z,t)$ +in a media parameterized by the speed of sound of $c(x,y,z)$ that is +spatially varying. + +The isotropic acoustic wave equation is: + +$$ p_{tt} = L(p,c) + s(x,y,z,t) , \quad L = c^2\nabla^2 p, s(x,y,z,t) = \delta(x-x')\delta(y-y')\delta(z-z')g(t)$$ + +subject to the homogeneous initial condition $p(x,y,z,0) = 0$. In the +above, $\nabla^2 p$ is the Laplacian of the pressure field and $g(t)$ is +a source term. The source term is to perturb the initial +pressure field such that waves are excited from a predetermined location +$(x',y',z')$. Over time, waves originating from the source propagate +throughout the domain. + +Theoretically, waves propagate to infinity or continue until vanishing. +Unfortunately, this is not applicable in modeling a particular region +because of the computational resources limitations. Therefore we truncate +the model to a region of interest along with boundary regions. +Absorbing all incoming energy at the boundaries of the computational +grid mimic a real-life infinite media. + +### Notes on boundary conditions + +Of great importance is the enforcement of boundary conditions. In +practice, the desired boundary condition is of an absorbing type that +mimics that of an unbounded medium. The truncation of the computational +domain introduces an artificial boundary that generates spurious +reflections that can pollute the solution in the interior of the +computational domain. So many absorbing boundary approaches were +developed to deal with this problem with trade-offs between accuracy, +and computational cost; some depend on physical attenuation like +random boundaries and some depend on artificial attenuation like +sponge and perfectly matched layers (PML). For our +purposes, we focus on interior discretizations and set aside boundary +treatments as their computational impacts are usually smaller +compared to the interior computation provided that the volume to surface +the ratio is large. + +## Discretization overview + +It is common to discretize the acoustic wave equation in two steps, +following a method of lines approach: + +1. The time integrator used is explicit in time and discretizes the + $p_{tt}$ term using 2nd-order leapfrog central discretization whereas + the right-hand side is evaluated at the current time step, $t_n$.\ +2. The spatial part is discretized using high-order finite differences, + typically 8th order. + +With a slight abuse of notation, the resulting temporal discretization +becomes + +$$ p^{n+1} - 2 p^n + p^{n-1} = \Delta t s(p^n, t^n)$$ + +In the above, it is understood that $p^n = p(x,y,z,t_n)$ and that +$t_n = \Delta t n$ is the $n$:th time step. + +### Main loop + +The following section demonstrates the main structure of an acoustic +wave equation solver. + +```c +for (int n = 0; n < nsteps; ++n) { + // Time step: t = n\Delta t + float t = n * dt; + // Solves p^{n+1} = -p^{n-1} + 2p^n + \Delta t L(p^n,t^n) + solve_acoustic_wave_equation(p_next, p_curr, p_prev, c_squared, dt); + // Treat snapshots + // Per each n cycles; store compressed or uncompressed snapshots + // Adds the discretization of the source term: s(x,y,z,t) evaluated at the grid index: si, sj, sk + apply_source(p_next, si,sj,sk, t); + // Cycle pointers to advance the pressure field for each time step + swap(p_prev , p_curr); +} +``` + +Note that this implementation stores the pressure field at only three +snapshots in time. In more detail, `p_next` corresponds to $p^{n+1}$, +`p_curr` corresponds to $p^n$, and `p_prev` corresponds to $p^{n-1}$. +The pointer-swapping technique is a simple way to avoid data movement +when advancing the wavefield. + +## Space discretization + +Most of the complexity that arises in the acoustic-iso seismic wave equation comes from the high +order discretization of the spatial part. For this +equation, it is necessary to discretize the Laplacian operator +$\\nabla\^2$ expressed in Cartesian coordinates, i.e., $\\nabla\^2 = +\\partial\^2\_{xx} + \\partial\^2\_{yy} + \\partial\^2\_{zz}$. + +### Multi-pass and one-pass approaches + +There are two types of approaches for discretizing the spatial part: the multi-pass approach and the one-pass one. These +approaches lie on opposite sides of the spectrum. In the multi-pass +approach, spatial derivatives are updated in multiple passes by operating in +one direction at a time. For example, the Laplacian operator can be +discretized by passing over the x-direction, then the y-direction, +and finally the z-direction. This is a *three-pass* approach. Here is an +example of this technique, demonstrated in pseudo-code for the Laplacian +operator only: + +```c +// split `p_out = \partial_x^2 p_in + \partial_y^2 p_in + \partial_z^2 p_in` into: +// p_out = \partial_x^2 p_in +compute_full_fd_d2(p_out, p_in, ...); +// p_out += \partial_y^2 p_in +compute_full_fd_d2(p_out, p_in, ...); +// p_out += \partial_z^2 p_in +compute_full_fd_d2(p_out, p_in, ...); +``` + +In this example, it is understood that the function +`compute_full_fd_d2(...)` handles the finite difference +discretization in the x-direction for all grid points. Likewise, +in the y-dim and z-dim, in each step incrementally update output field array. + +The disadvantage of this *three-pass* approach is that it requires +multiple trips to main memory, over the same data, to perform the +computation. In this case, `p_in` needs to be read three times and +`p_out` needs to be read two times and written three times. Since +seismic stencils are typically bandwidth-bound, these extra trips to +main memory can become quite costly from a performance standpoint. When +performance is important, it is generally recommended to implement a +*one-pass* approach. However, a major advantage of the multi-pass +approach is its simplified implementation because it processes +one grid direction at a time. This aspect becomes apparent if e.g., the +finite difference discretization changes at the boundary. In this case, +it could be necessary to alter the computation near the boundary. As a result, there would be three +different types of computations per grid direction. However, if all of +the grid directions are processed in a single pass it would be necessary +to do 3\^3 = 27 different computations. + +At the opposite end of the spectrum is the *one-pass approach*. As the +name suggests, the one-pass approach uses a single function to compute +the entire Laplacian operator at once. + +```c +// Compute the entire Laplacian: p_out = \partial_x^2 p_in + \partial_y^2 p_in + \partial_z^2 p_in +compute_full_fd_laplacian(p_out, p_in, ...); +``` + +This technique was used to discretize spatial operators in our blog +[here](../../finite-difference/docs/Laplacian_Part1.md). While this approach minimizes the number of trips to main +memory, it typically requires more GPU hardware resources, i.e., +registers and shared memory as compared to multi-pass approaches. Since +the one-pass approach packs more work into a single kernel, it gives the +compiler more opportunities to optimize the code, and the number of +hand-crafted optimizations that one can perform dramatically increase +as well. + +For our purposes, we are going to demonstrate some of the popular +techniques focusing on taking a multi-pass approach. We have made this +choice because it simplifies the forthcoming presentations. However, it +should be noted that these techniques should in most cases be extended +to one-pass approaches to obtain the best possible performance that the +hardware can deliver. + +### High order finite difference approximations + +Here are some high-order finite difference approximations of second +derivative terms of the Laplacian applied at the grid point +$(x_i, y_j, z_k)$ with uniform grid spacing $h_x, h_y, h_z$ in each grid-direction: + +$$ +\partial^2_{xx} p \approx \sum_{r=-R}^{R} \frac{d_{r}}{h_x^2} p(x_i + r h_x, y_j, z_k,t), \ +\partial^2_{yy} p \approx \sum_{r=-R}^{R} \frac{d_{r}}{h_y^2} p(x_i, y_j + rh_y, z_k,t), \ +\partial^2_{zz} p \approx \sum_{r=-R}^{R} \frac{d_{r}}{h_z^2} p(x_i, y_j, z_k + rh_z,t). +$$ + +In the approximations above, the stencil has a radius $R$, and the width of +the stencil is $2R + 1$ grid points wide. If the stencil is symmetric, +$d_r = d_{-r}$, then it is possible to construct difference +approximations of $2R$ in order of accuracy.For $R=1$, the symmetric second +order accurate coefficients are: $d_{-1} = d_{1} = 1$ and $d_{0} = -2$. +Higher orders are tabulated +[here](https://en.wikipedia.org/wiki/Finite_difference_coefficient). For +seismic applications, $R$ is typically at least $4$ (8th order) or more. + +The following example code applies a high-order finite difference +operator to `nx * ny * nz` interior grid points in a given direction. + +```c +template +__inline__ void compute_d2(float *p_out, const float *p_in, const float *d, const int R, int pos) { + /* Computes a central high-order finite difference approximation in a given direction + p_out: Array to write the result to + p_in: Array to apply the approximation to + d: Array of length 2 * R + 1 that contains the finite difference approximations, including scaling by grid spacing. + R: Stencil radius + pos: The current grid point to apply the approximation to + stride: The stride to use for the stencil. This parameter controls the direction in which the stencil is applied. + */ + float out = 0.0f; + for (int r = -R; r < R; ++r) + out += d[r + R] * p_in[pos + r * stride]; + } + p_out[pos] += out; +} +``` + +This example code uses floating-point single precision because this +level of precision is arguably the most widely used choice in practice. + +When implementing the high-order finite difference method, it is +convenient to pad the arrays to leave room for halo regions. The halo +regions could be occupied by neighbors or boundary values for imposing +boundary conditions. + +```c +// Interior grid size +int nx, ny, nz; +nx=ny=nz=10; +// Padded grid size +int mx = nx + 2 * R; +int my = ny + 2 * R; +int mz = nz + 2 * R; +uint64_t m = mx * my * mz; +float *p_out = new float[m]; +float *p_in = new float[m]; +``` + +Since the input and output arrays are collapsed into one dimension, the +variable `pos` specifies how to linearly access grid value at a grid point +$(x_i, y_j,z_k)$ via the formula: + +```c +pos = i + line * j + slice * k; +``` + +If the leading dimension of the array is taken along the x-direction, +then + +```c +int line = nx + 2 * R; +int slice = line * (ny + 2 * R); +``` + +The listing below demonstrates the application of the high-order finite +difference method. + +```c +const float h = 0.1; +const int R = 1; +const float d[2*R + 1] = {1.0 / (h * h), -2.0 / (h * h), 1.0 / (h * h)}; + +// Define each direction to apply the finite difference approximation in +const int x = 1; +const int y = line; +const int z = stride; + +const int line = mx; +const int slice = mx * my; +const uint64_t n = mx * my * mz; + +// zero-initialize the memory +memset(p_out, 0, n * sizeof(float)); + +// Apply approximation in the x-direction for all interior grid points +for (int k = R; k < nz + R; ++k) { + for (int j = R; j < ny + R; ++j) { + for (int i = R; i < nx + R; ++i) { + const uint64_t pos = i + line * j + slice * k; + compute_d2(p_out, p_in, d, R, pos, line, slice); + } + } +} +``` + +By changing the `stride` parameter, the code can easily be changed into +a finite difference approximation of a particular direction. + +```c +// Apply approximation in the x-direction +compute_d2(p_out, p_in, d, R, pos, line, slice); +// Apply approximation in the y-direction +compute_d2(p_out, p_in, d, R, pos, line, slice); +// Apply approximation in the z-direction +compute_d2(p_out, p_in, d, R, pos, line, slice); +``` + +## Baseline kernels + +It is now time to take a look at high-order finite difference +approximations on the GPU. As a starting point, let us consider a simple +kernel that applies the finite difference method in the x-direction. +This kernel will be used for all future performance comparisons. + +``` cpp + // Table containing finite difference coefficients + template __constant__ float d_dx[2 * R + 1]; + template __constant__ float d_dy[2 * R + 1]; + template __constant__ float d_dz[2 * R + 1]; + + template + __launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y) * (BLOCK_DIM_Z)) + __global__ void compute_fd_x_gpu_kernel(float *__restrict__ p_out, const float *__restrict__ p_in, + int line, int slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int i = x0 + threadIdx.x + blockIdx.x * blockDim.x; + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + + if (i >= x1 || j >= y1 || k >= z1) return; + + size_t pos = i + line * j + slice * k; + int stride = 1; // x-direction + + // Shift pointers such that that p_in points to the first value in the stencil + p_in += pos - R * stride; + p_out += pos; + + // Compute the finite difference approximation + float out = 0.0f; + for (int r = 0; r <= 2 * R; ++r) + out += p_in[r * stride] * d_dx[r]; // x-direction + + // Write the result + p_out[0] = out; + + } +``` + +The above kernel can be modified to compute stencils in the y-direction +and z-direction with `int stride = line;` and `int stride = slice;`, +respectively. This kernel uses `x0,y0,z0` and `x1,y1,z1` to define the +region of interest to apply the stencil. Defining the bounds in such +a way is convenient because it gives explicit control over where to apply +the stencil. If there is a need to overlap communication and +computation, the same kernel can be called multiple times with arguments +that map to e.g., different halo slices. To restrict attention to all +interior points, the bounds need to be `x0=R`, `x1=nx+R`, `y0=R`, +`y1=ny+R`, `z0=R`, `z1=nz+R`. In the kernel, the indices `i`,`j`,`k` are +shifted by `x0`,`y0`,`z0`. This shift saves three comparison +instructions because it removes the lower bounds check and also +avoids having some idle threads outside the lower bounds. On the other +hand, the shift in the x-direction can negatively impact performance due +to unaligned memory accesses. + +## Initial performance + +Let us quickly assess the performance of these baseline kernels using two different figure of merits (FOM). +First, like in the [Laplacian series](../../finite-difference/docs/Laplacian_Part1.md), we understand from +the stencil algorithm design that each grid point need only be loaded once and is reusable by +neighboring threads. Hereby, we shall use the *effective memory bandwidth* defined as: + +```c++ +effective_memory_bandwidth = (theoretical_fetch_size + theoretical_write_size) / average_kernel_execution_time; +``` + +where the theoretical fetch and write sizes (in bytes) of an `nx * ny * nz` cube are: + +```c++ +theoretical_fetch_size = (nx * ny * nz + 2 * R * PLANE) * sizeof(float); +theoretical_write_size = (nx * ny * nz) * sizeof(float); +``` + +where `PLANE` is `ny * nz`, `nx * nz`, and `ny * nz` for the x-direction, y-direction, and z-direction, respectively. +Ideally, we want this FOM to be a close to the achievable memory bandwidth as possible. On a single MI250X GCD, +these are the *effective memory bandwidth*[^1] numbers on a 512 x 512 x 512 cube for various values of `R`: + +| Radius (R) | x-direction | y-direction | z-direction | +|------------|:-----------:|:-----------:|:-----------:| +| 1 | 971 GB/s | 948 GB/s | 915 GB/s | +| 2 | 995 GB/s | 982 GB/s | 753 GB/s | +| 3 | 977 GB/s | 965 GB/s | 394 GB/s | +| 4 | 956 GB/s | 940 GB/s | 217 GB/s | + +Both larger stencil radii and larger strides in memory worsen the bandwidth. +All of these numbers, including the smaller stencil radii and strides, fall +significantly short of the achievable bandwidth of a single MI250X GCD, which according to the +[BabelStream case studies](https://www.olcf.ornl.gov/wp-content/uploads/2-16-23-node_performance.pdf) +is roughly 1.3 TB/s to 1.4 TB/s. However, these FOMs alone do not offer insight +into how well our GPU implementations are utilizing the hardware. + +Therefore, we provide the *achieved memory bandwidth* which is attainable using two different approaches. The first approach is to +use `rocprof` directly and take the sum of the `FETCH_SIZE` and `WRITE_SIZE` metrics divided by the average kernel execution time. +The second approach is to use [omniperf](https://amdresearch.github.io/omniperf/) and take the sum of the reported `L2-EA Rd BW` and `L2-EA Wr BW`. +Ideally we also want this number to be as close to the achievable memory bandwidth as possible. +Below are the corresponding achieved memory bandwidth numbers[^1]: + +| Radius | x-direction | y-direction | z-direction | +|---------|:-----------:|:-----------:|:-----------:| +| 1 | 976 GB/s | 953 GB/s | 931 GB/s | +| 2 | 1003 GB/s | 995 GB/s | 953 GB/s | +| 3 | 986 GB/s | 981 GB/s | 925 GB/s | +| 4 | 967 GB/s | 959 GB/s | 891 GB/s | + +Both the x-direction and y-direction present achieved memory bandwidth numbers that align closely with +the reported effective memory bandwidth. When both the effective and achieved memory bandwidth numbers align, +this indicates that the amount of data, i.e., the numerator, moved is the same. Both bandwidth +metrics use the same kernel execution time, so if both bandwidth metrics are low, this suggests +that either a portion of the kernel is compute-heavy and not fully overlapped with memory transfers +and/or there are underlying latency issues. + +However, the z-direction appears to have a much higher achieved memory +bandwidth, suggesting that while the hardware utilization may be better +than the x and y direction implementations, the kernel is fetching from and/or +writing to global memory much more than ideal. + +## Conclusion + +This concludes the first part of developing seismic stencil codes that often +rely on the discretization of the wave equation using high-order +finite difference methods. We first begin with the three-pass approach +and present initial performance numbers for varying stencil radii and +directions. None of the implementations show satisfactory +performance in either the effective or achieved memory bandwidths, +and the next series of posts shall dive into possible +optimizations to elevate the memory bandwidth numbers. + +[Accompanying code examples](https://github.com/amd/HPCTrainingExamples/tree/main/rocm-blogs-codes/seismic-stencils) + +If you have any questions or comments, please reach out to us on +GitHub [Discussions](https://github.com/amd/amd-lab-notes/discussions) + +[^1]:Testing conducted using ROCm version 6.1.0-82. Benchmark results are not +validated performance numbers, and are provided only to demonstrate relative +performance improvements of code modifications. Actual performance results +depend on multiple factors including system configuration and environment +settings, reproducibility of the results is not guaranteed. diff --git a/blogs/high-performance-computing/seismic-stencils/part-2/README.md b/blogs/high-performance-computing/seismic-stencils/part-2/README.md new file mode 100644 index 0000000..e49b923 --- /dev/null +++ b/blogs/high-performance-computing/seismic-stencils/part-2/README.md @@ -0,0 +1,552 @@ +--- +blogpost: true +date: 29 Aug 2024 +author: Justin Chang, Ossian O'Reilly +tags: HPC, Memory, Performance, Profiling, Optimization, Scientific Computing +category: Applications & models +language: English +myst: + html_meta: + "description lang=en": "Seismic Stencil Codes - Part 1" + "keywords": "HPC, finite difference, Seismic, PDE, MI250, performance" + "property=og:locale": "en_US" +--- + +# Seismic stencil codes - part 2 + +12 Aug, 2024 by {hoverxref}`Justin Chang` and {hoverxref}`Ossian O'Reilly`. + +In the previous post, recall that the kernel with stencil computation in the z-direction suffered +from low effective bandwidth. This low performance comes from generating substantial amounts +of data to movement to global memory. To address this performance bottleneck, we will consider +two optimizations, one that trades off memory footprint for improved performance, +and another one that diverts pressure away from the memory subsystem and places more +of the pressure on the GPUs vector registers. For simplicity, all experiments +use a cubic grid size `nx, ny, nz = 512, 512, 512` and stencil radius `R=4`. + +## Aligned vs unaligned memory accesses + +The first optimization aligns memory accesses so that each wave in a thread block +writes to a complete set of cache lines. To align the memory accesses, pad the leading +dimension and offset the base pointers. The leading dimension should be a multiple +of the cache line size. Otherwise, the organization of cache lines changes depending +on which line or slice of the computational grid is accessed. The figure below demonstrates +how an excessive number of cache lines can get accessed in an unaligned case (left) and +how the optimal number of cache lines is accessed with a proper offset and padding. + + + +

+Figure 1: Unaligned and aligned cache line accesses for a 2D array. +(left) Unaligned accesses and (right) aligned accesses. Each shaded +box in light blue represents a cache line. +

+ +Here, we pad the leading dimension such that it is always divisible by 64. + +```c++ +int align = 64; +// Define mx = nx + 2 * R and pad it by some amount such that mx is divisible +// by 'align' +int mx = nx + 2 * R; +int mx = ((mx - 1) /align + 1) * align; +``` + +Naturally, another option is to restrict the grid size to be a multiple of the wave size, +if possible. This strategy can lead to further performance improvements as it also ensures +that all threads in wave are fully utilized, i.e., leaving no idle threads near the boundary. + +To ensure aligned memory accesses without changing the kernel itself, we offset the base pointers + +```c++ +int offset = align - R; +hipMalloc(&d_p_in, (mx * (ny + 2 * R) * (nz + 2 * R) + offset) * sizeof(float)); +hipMalloc(&d_p_out, (mx * (ny + 2 * R) * (nz + 2 * R) + offset) * sizeof(float)); +d_p_in += offset; +d_p_out += offset; +``` + +This offset assumes that the input argument that specifies the starting index +in the x-direction for the baseline kernel is `x0=R`. Recall the baseline kernel +implementation: + +```cpp + template + __launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y) * (BLOCK_DIM_Z)) + __global__ void compute_fd_x_gpu_kernel(float *__restrict__ p_out, const float *__restrict__ p_in, + int line, int slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int i = x0 + threadIdx.x + blockIdx.x * blockDim.x; + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + + if (i >= x1 || j >= y1 || k >= z1) return; + + size_t pos = i + line * j + slice * k; + int stride = 1; // x-direction + + // Shift pointers such that that p_in points to the first value in the stencil + p_in += pos - R * stride; + p_out += pos; + + // Compute the finite difference approximation + float out = 0.0f; + for (int r = 0; r <= 2 * R; ++r) + out += p_in[r * stride] * d_dx[r]; // x-direction + + // Write the result + p_out[0] = out; + + } +``` + +### Baseline performance + +Next, we demonstrate the performance implications of aligned vs unaligned memory accesses. +In this experiment, all settings remain the same except for whether memory +accesses are aligned or not. When the accesses are aligned, the arrays are padded such that +the leading dimension is divisible by 64 elements and the base pointers are offset by 60 +elements for the radius `R=4`. The table below shows that proper alignment of the memory +accesses can have a significant impact on performance for AMD Instinct MI200 series GPUs. + +|Kernel |Effective memory bandwidth | Speedup | +|---|---|---| +| x-direction: Unaligned | 956 GB/s | 1.00 | +| x-direction: Aligned | 990 GB/s | 1.04 | +| y-direction: Unaligned | 940 GB/s | 1.00 | +| y-direction: Aligned | 966 GB/s | 1.03 | +| z-direction: Unaligned | 217 GB/s | 1.00 | +| z-direction: Aligned | 297 GB/s | 1.37 | + +It should be mentioned that the aligned version uses slightly more memory due +to the array padding. For a 512 x 512 x 512 cube, this increase in memory consumption +is $\approx 10\%$ . On the other hand, the effective memory bandwidth improves by up to 1.37x. + +At the L1, and L2 cache levels, the aligned memory access pattern reduces the +number of requests compared to the unaligned case. This is +because without aligned memory accesses, the data requested by a wave can be +spread across both full and partial cache lines. The caches operate at their +cache line granularity, meaning that any partial cache line requests still +need to be serviced by allocating and moving full cache lines into the caches. +Since the partial cache lines also need to be accessed by neighboring thread +blocks, they are reused if they are cached in L2. As a result, we +should expect to see to an insignificant difference in data movement from main/global +memory (referred to as High Bandwidth Memory or HBM for MI250) when toggling alignment on/off. You can see +these behaviors by collecting the following performance counters: + +| Performance counter | Description | +|---------------------|-------------| +| `TCP_TOTAL_CACHE_ACCESSES_sum` | The total number of cache line accessed in the L1 cache. | +| `TCP_TCC_READ_REQ_SUM` | The total number of read requests that missed in L1 and went to the L2 cache. | +| `TCP_TCC_WRITE_REQ_SUM` | The total number of write requests that missed in L1 and went to the L2 cache. | + +To convert the number of requests into the amount of data they moved in bytes, +multiply them by 64 B - the MI250 L1 cache line size. + +|Kernel|L1|L2 read|L2 write|HBM| +|---|---|---|---|---| +| x-direction: Unaligned | 7247 MB | 570 MB | 671 MB | 1088 MB | +| x-direction: Aligned | 6979 MB | 604 MB | 537 MB | 1105 MB | +| y-direction: Unaligned | 10737 MB | 2009 MB | 671 MB | 1097 MB | +| y-direction: Aligned | 5369 MB | 1610 MB | 537 MB | 1080 MB | +| z-direction: Unaligned | 10737 MB | 6040 MB | 671 MB | 4447 MB | +| z-direction: Aligned | 5369 MB | 4832 MB | 537 MB | 4268 MB | + +To gain further insight into the amount of data moved throughout +the memory subsystem, divide each data entry in the table above by the +cube size `(512 * 512 * 512) * sizeof(float)` which is +approximately 536 MB. See the new ratios: + +|Kernel|L1|L2 read|L2 write|HBM| +|---|---|---|---|---| +| x-direction: Unaligned | 13.5 | 1.06 | 1.25 | 2.03 | +| x-direction: Aligned | 13.0 | 1.13 | 1.00 | 2.06 | +| y-direction: Unaligned | 20.0 | 3.75 | 1.25 | 2.05 | +| y-direction: Aligned | 10.0 | 3.00 | 1.00 | 2.01 | +| z-direction: Unaligned | 20.0 | 11.3 | 1.25 | 8.30 | +| z-direction: Aligned | 10.0 | 9.00 | 1.00 | 7.96 | + +This number represents the number of cubes that passes through each level +of the memory hierarchy. For both the x-direction and y-direction +kernels, roughly two cubes move between the L2 cache and HBM. This case is +the ideal scenario because it corresponds to reading and writing a cube once. +However, we notice from the L1 and L2 caches that up to 20 cubes worth of data is +processed. Ideally we want these cubes loaded and stored +as little as possible, which alignment appears to reduce. The next sub sections +will analyze this phenomena for each direction. + +#### X-direction accesses + +The small difference between the aligned and unaligned HBM data movement +shows that the alignment optimization primarily impacts the number of cache +lines moved through the caches. For the x-direction kernel, most stencil +neighboring accesses hit on the same cache line regardless whether the +data is cache-line aligned or not (Fig. 2). As a result, there is small +difference in data movement across all levels of the memory subsystem. + + + +

+Figure 2: Due to the halo region of radius R, partial cache lines need to + be loaded at the thread block boundaries in the x-direction regardless + whether the data is cache line-aligned or not. +

+ + + +

+Figure 3: The number of cache lines accessed when loading the neighboring + values in the unaligned case can be the same as the aligned case or one + cache line less, depending on the cache line boundary location. +

+ +#### Y-direction accesses + +In contrast, for the y kernel, each neighboring access hits on a different cache line. +Without alignment, the number of accessed cache lines per thread block is much greater +compared to the aligned case (Fig. 3 and Fig 4.). + + + +

+Figure 3: The figure shows the cache lines that a group of threads along the bottom +edge of a thread block need to access to compute the stencil in the y-direction +(only the bottom half of the neighbors are shown). Each neighbor access in the +y-direction hits on a different cache line. Since the data is aligned, all cache +lines are collinear and that minimizes the number of accesses needed when +computing the y-direction stencil using the cache. +

+ + + +

+Figure 4: Same as (Fig. 3) but with unaligned data. In this case, the y-direction +stencil computation accesses an additional cache line for each row of neighbors in the y-direction. +

+ +#### Z-direction accesses + +While the aligned z-direction kernel saturates main memory bandwidth too a high degree, +the kernel's performance is far away from its limits. Since the kernel only +loads and writes two arrays in the ideal case, the optimal read-to-write ratio should be close +to unity. The x and y direction kernels are already close to this optimal limit +but the z-direction kernel is nowhere close: + +|Kernel|HBM Read / Write| +|---|---| +| x-direction: Unaligned | 1.01 | +| x-direction: Aligned | 1.07 | +| y-direction: Unaligned | 1.02 | +| y-direction: Aligned | 1.02 | +| z-direction: Unaligned | 7.05 | +| z-direction: Aligned | 7.02 | + +> **Note:** As noted in [Part 4](../../finite-difference/docs/Laplacian_Part4.md) of the Finite Difference Laplacian blog series, +> an xy-plane of a 512 x 512 x 512 cube fits into the L2 cache of a single MI250X +> GCD so there is some reuse, hence why the z-direction read / write ratio is 7.0 +> and not 9.0. In our experimentation not shown in this blog post, a 1024 x 1024 x 1024 +> cube indeed has a read / write ratio of 9.0 + + + +

+Figure 5: The stencil in the z-direction suffers from excessive HBM data +movement due to poor data reuse. The thread blocks are 2-D and all of +the currently active blocks running on the device fall within a narrow +band of the cube (the active compute set in the figure). The thread +blocks load the halo data above and below them into the L2 cache. +The L2 cache is not large enough to hold multiple slices of data. +By the time a thread block computes below a thread block, the data +has most likely been evicted from the cache. As a result, the data +needs to be reloaded once more from HBM. +

+ +This massive amount of excess reads for the z-direction come from nearly no data reuse in +the stencil computation (Fig 5). Recall that the stencil computation needs to +load 8 neighboring values. Ideally, these values should be loaded from +caches or registers instead of main memory. The reason they do not +persist in the L2 cache for reuse is due to the current kernel implementation, +thread block configuration, and problem size. In the current thread block +configuration, the threads are layed out in a 2D pattern. So, there are +no waves in the thread block in the vertical direction, and therefore +there are no neighboring waves in the vertical direction that share data +via either the L1 or L2 caches. The second reason is because the problem +size is large enough to keep the entire device busy with thread blocks +that work on the same vertical slice. Thus, any data that any thread +block loads into L2 is highly unlikely to be reused because it would +require a thread block working on a slice either immediately below or +above it. For these reasons, there is little data in the L2 cache +that can be reused by other thread blocks (hence the 7.0 read / write ratio +noted above). While it is possible to +mitigate the situation to some extent by choosing another thread +block size, we are going to address it by changing the algorithm. + +Since the z-direction stencil computation is the worst performing kernel, +the next optimization will focus solely on improving its performance. + +## Sliding window + +The z-direction kernel demonstrated one of the key challenges that arise +when implementing high order finite differences. Namely, how to +effectively reuse data during the stencil computation. To achieve +outstanding performance, it is important to avoid expensive loads that +go to global memory. Fortunately, the type of stencil patterns that +emerge from high order finite differences have a repeating pattern that +can be handled using a sliding window technique (Fig. 6) + + + +

+Figure 6: The key idea behind the sliding window technique for +stencil computation is to hold a local volume of the input array +data in registers and compute the stencil in the z-direction +entirely using these registers. To compute the stencil for the +next z-value, it is sufficient to load only one more slice of +data of the data into registers and re-use the previous data +found in registers from before. +

+ +The sliding window algorithm can be implemented in four steps: + +1. Load all of values in the stencil except for the last one into an + array of registers +2. Load the last value in the stencil into the register array +3. Compute the FD approximation using all of the values in the register + array +4. Update the sliding window by shifting it forward one step, + overwriting the previous first value in the register array + +Repeat steps 2 - 4 for each grid point that the sliding window updates. +See the below images for a pictorial description of the above steps assuming +`R=4` and an input array `p[i]` initialized with `p[i] = i * i` : + + + +

+Figure 7: Step 1 - priming the window by loading the first 8 values +

+ + + +

+Figure 8: Steps 2 and 3 - loading the last value of the window, computing the finite difference, +and storing the result +

+ + + +

+Figure 9: Step 4 - updating the sliding window +

+ + + +

+Figure 10: Repeat steps 2 through 4 with the newly shifted sliding window +

+ +The sliding window reduces the number of main memory load instructions +for $N$ updates from $(2R+1)*N$ to $2R + N$ at the price of needing +$2R+1$ registers. + +Here is a sliding window implementation of the high order stencil +function we saw before: + +```c++ +template +__inline__ void compute_fd_z_sliding_window(float *p_out, const float *p_in, const float *d, + int begin, int end, int pos, int stride) { + // Sliding window + float w[2 * R + 1]; + + // 1. Prime the sliding window + for (int r = 0; r < 2 * R; r++) + w[r] = p_in[pos + (begin - R + r) * stride]; + + // Apply the sliding window along the given grid direction determined by `stride` + for (int i = begin; i < end; ++i) { + + // 2. Load the next value into the sliding window at its last position + w[2 * R] = p_in[pos + (i + R) * stride]; + + // 3. Compute the finite difference approximation using the sliding window + float out = 0.0f; + for (int r = 0; r <= 2 * R; r++) + out += w[r] * d[r]; + p_out[pos + i * stride] = out; + + // 4. Update the sliding window by shifting it forward one step + for (int r = 0; r < 2 * R; r++) + w[r] = w[r+1]; + + } +} +``` + +This function can be used as follows for computing the sliding window in +the z-direction: + +```c++ +// Apply approximation in the x-direction for all interior grid points +for (int j = R; j < ny + R; ++j) { + for (int i = R; i < nx + R; ++i) { + const uint64_t pos = i + line * j; + compute_fd_z_sliding_window(p_out, p_in, d, R, nz + R, pos, slice); + } +} +``` + +### Sliding window on the GPU + +The GPU-based sliding window implementation shares many similiaries with +the host-based implementation. Here it is: + +```c++ +template +__launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y)) +__global__ void compute_fd_z_window_kernel(float *p_out, const float *p_in, const float *d, int line, int + slice, int x0, int x1, int y0, int y1, int z0, int z1, int dimz) { + + const int i = x0 + threadIdx.x + blockIdx.x * blockDim.x; + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + + if (i >= x1 || j >= y1) return; + + // Determine the k indices covered by this sliding window + // The extent cannot exceed the z1 + const int kbegin = z0 + blockIdx.z * dimz; + const int kend = kbegin + dimz > z1 ? z1 : kbegin + dimz; + + // Sliding window + float w[2 * R + 1]; + + size_t pos = i + line * j + slice * kbegin; + + // Shift pointers such that that p_in points to the first value in the sliding window + p_in += pos - R * slice; + p_out += pos; + + // 1. Prime the sliding window + for (int r = 0; r < 2 * R; ++r) { + w[r] = p_in[0]; + p_in += slice; + } + + // Apply the sliding window along the given grid direction + for (int k = kbegin; k < kend; ++k) { + + // 2. Load the next value into the sliding window at its last position + w[2 * R] = p_in[0]; + + // 3. Compute the finite difference approximation using the sliding window + float out = 0.0f; + for (int r = 0; r <= 2 * R; ++r) + out += w[r] * d_dz[r]; + p_out[0] = out; + + // 4. Update the sliding window by shifting it forward one step + for (int r = 0; r < 2 * R; ++r) + w[r] = w[r+1]; + + // Increment pointers + p_in += slice; + p_out += slice; + } +} +``` + +In this implementation, the thread block configuration must be 2D and +the threads layed out in the XY-plane. Each thread in a thread +block is responsible for computing a sliding window that starts from +`kbegin` and finishes at `kend-1`. +These start and end points depend on +the number of grid points a thread block should update in the +z-direction. In this implementation, each thread block slides over the +same number of grid points, $n_w$, except for thread blocks near the +boundaries if the work is not evenly divisible by the grid size. + +As previously explained, while the thread block dimension is 2D, the +thread blocks cover a 3D thread block grid. The kernel is launched via: + +```c++ + dim3 block(BLOCK_DIM_X, BLOCK_DIM_Y); + dim3 grid; + grid.x = ceil(x1 - x0, block.x); + grid.y = ceil(y1 - y0, block.y); + grid.z = ceil(z1 - z0, nw); + + compute_fd_z_window_kernel<<>>(p_out, p_in, d, line, slice, x0, x1, + y0, y1, z0, z1, nw); +``` + +### Performance considerations + +The parameter $n_w$ that controls the number of grid points that a +thread block slides over can have major performance implications. If +$n_w=1$, the sliding window degenerates to the baseline kernel that only +updates one grid point per thread. In this case, we know that the number +of load instructions explodes to $(2R+1)n_z$. On the other hand, this +choice exposes $n_z$ amount of parallelism. In the opposite limit, +$n_w=n_z$, the number of load instructions is $2R + n_z$, but there is +no parallelism exposed in the z-drection. In the general case, the +number of load instructions is $(2R + n_w)n_z/n_w$ and $n_z / n_w$ is +the parallelism exposed. Hence, depending on the problem dimensions, +there can be a trade-off between reducing the number of load +instructions and exposing a sufficient amount parallelism to saturate +the hardware resources. If we assume that the reduction in parallelism +is negligible, then an upper bound on the speedup is the ratio of the +number of load and stores of the baseline kernel to the optimal number: +$S \leq (1 + (2R + 1))/(1 + 1) = R+1$. For $R=4$, the speedup is at most +5x. + + + +

+Figure 11: The sliding window kernel exhibits up to an effective memory bandwidth of +1200 GB/s[^1], which is roughly a 4x speedup over the baseline kernel. This speedup comes from reducing the +read/write ratio by roughly 7x. +

+ +In the figure above, the left sub-panel shows both the effective and achieved +memory bandwidths as a function of the window dimension, $n_w$ on a semi log scale. +There is a point of diminishing returns for the effective bandwidth. This point occurs when +there is little change in the HBM read - write ratio for increasing $n_w$. +The right sub-panel shows the HBM read - write ratio comparing the predicted vs achieved +results. Recall from our earlier discussion that due to the size of the xy-plane, there is +come reuse in the L2 cache hence why the achieved value is 7.0 compared to the predicted +value of 9.0. Either way, both curves approach near unity. + +Due to the trade-off between increasing parallelism and decreasing +read-write ratio, the maximum speedup is about 4x instead of 5x. In +our experiment, the decrease in exposed parallelism gradually decreases +the achieved bandwidth. Both the achieved and effective memory bandwidths for the +z-direction kernel are now close to 1200 GB/s[^1]. + +## Conclusion + +Cache line alignment can be an important optimization to consider for stencil computation +because it reduces the number of cache line accesses. For any stencil computation leveraging +the cache, it is important to use a thread block configuration that encourages a high degree +of data re-use of the stencil's neighboring values. For the stencils in the z-direction, +if the problem size is large enough and the thread block is 2-D, then there can be little +to no data re-use. This issue emerges because the cache is not large enough to hold the +number of slices of the data required for caching the stencil neighbors in the z-direction. +As a result, HBM data movement gets inflated and performance drops dramatically. An +effective way to address this problem on AMD GPUs is to use a sliding thread block +technique. When the sliding thread block technique is combined with the alignment +optimization it results in nearly a 5.5x speedup improvement over the naive, baseline +case. Another way to further reduce the number of global memory requests is to use +the user-programmable cache, the so-called local data share (LDS). The next blog +post will focus on this topic for the x-direction, and y-direction kernels, as well +as combining all three kernels into a single monolithic one. + +[Accompanying code examples](https://github.com/amd/HPCTrainingExamples/tree/main/rocm-blogs-codes/seismic-stencils) + +If you have any questions or comments, please reach out to us on +GitHub [Discussions](https://github.com/amd/amd-lab-notes/discussions) + +[^1]:Testing conducted using ROCm version 6.1.0-82. Benchmark results are not +validated performance numbers, and are provided only to demonstrate relative +performance improvements of code modifications. Actual performance results +depend on multiple factors including system configuration and environment +settings, reproducibility of the results is not guaranteed. diff --git a/blogs/high-performance-computing/seismic-stencils/part-3/README.md b/blogs/high-performance-computing/seismic-stencils/part-3/README.md new file mode 100644 index 0000000..5c93ecf --- /dev/null +++ b/blogs/high-performance-computing/seismic-stencils/part-3/README.md @@ -0,0 +1,764 @@ +--- +blogpost: true +date: 29 Aug 2024 +author: Justin Chang, Ossian O'Reilly +tags: HPC, Memory, Performance, Profiling, Optimization, Scientific Computing +category: Applications & models +language: English +myst: + html_meta: + "description lang=en": "Seismic Stencil Codes - Part 1" + "keywords": "HPC, finite difference, Seismic, PDE, MI250, performance" + "property=og:locale": "en_US" +--- + +# Seismic stencil codes - part 3 + +12 Aug, 2024 by {hoverxref}`Justin Chang` and {hoverxref}`Ossian O'Reilly`. + +In the last two blog posts, we developed a HIP kernel capable of computing +high order finite differences commonly needed in seismic wave propagation. +The optimizations enabled the z-direction kernel, the worst performing +kernel based on our initial implementation, to achieve both an achieved +and effective memory bandwidth close to 1200 GB/s[^1] on a single GCD of a MI250X. +This performance corresponds to 85 % of the achievable memory bandwidth, see [^2]. +In this third and final part of the seismic +stencil blog series, we optimize the x-direction and y-direction kernels to +boost their performances as well. Afterwards, we +fuse all three kernels into a single monolithic kernel following the *one-pass approach* +briefly mentioned in the first part of this blog series. + +Recall from [Part 1](./seismic-stencils-part1.md) the baseline implementation: + +```c++ + template + __launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y) * (BLOCK_DIM_Z)) + __global__ void compute_fd_x_kernel(float *__restrict__ p_out, const float *__restrict__ p_in, + int line, int slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int i = x0 + threadIdx.x + blockIdx.x * blockDim.x; + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + + if (i >= x1 || j >= y1 || k >= z1) return; + + size_t pos = i + line * j + slice * k; + int stride = 1; // x-direction + + // Shift pointers such that that p_in points to the first value in the stencil + p_in += pos - R * stride; + p_out += pos; + + // Compute the finite difference approximation + float out = 0.0f; + for (int r = 0; r <= 2 * R; ++r) + out += p_in[r * stride] * d_dx[r]; // x-direction + + // Write the result + p_out[0] = out; + + } +``` + +The amount of memory traffic at the L1, L2 and HBM +memory levels (with memory alignment such that the leading dimension x is padded by 64) for a 512 x +512 x 512 problem size is: + +|Kernel|L1|L2 read|L2 write|HBM| +|---|---|---|---|---| +| x-direction: Memory | 6979 MB | 604 MB | 537 MB | 1105 MB | +| x-direction: Memory / cube ratio | 13.0 | 1.13 | 1.00 | 2.06 | +| y-direction: Memory | 5369 MB | 1610 MB | 537 MB | 1080 MB | +| y-direction: Memory / cube ratio | 10.0 | 3.00 | 1.00 | 2.01 | + +While the HBM and L2 write ratios report levels we expect (i.e., approximately +2 cubes of movement at the HBM level and 1 cube written from L2), the L1 +cache access is undesirably high. This excessive data movement through L1 is a potential +reason why both the effective and achieved memory bandwidths both sit under 1 TB/s[^1] +despite up to 1.3 to 1.4 TB/s being possible for simple streaming benchmarks. The next two +optimizations explores techniques aimed at reducing this traffic. Again, we perform all experiments +on a 512 x 512 x 512 cube and `R=4` on a single MI250X GCD. Memory alignment and offsets are +enforced such that the leading dimension x is divisible by 64. + +## Optimization 1 - vectorized floats + +In our finite difference Laplacian series (see [here](../../finite-difference/docs/Laplacian_Part2.md)), +we introduced the idea of loop unrolling which widens the tile size and increases data reuse through registers. +We shall apply something similar here by leveraging vectorized floats. The idea behind this +technique is to widen the tile size in the x-direction via vector instructions. As a result, each +thread in a thread block is responsible for computing one, two, or four output elements, depending +on the vector size. Naturally, vector instructions increase the register pressure per thread, which +may hurt occupancy. However, a benefit of the vector instructions is that they leverage the fact +that the hardware is capable of requesting data that is up to 128-bits per lane for global memory +load and store instructions. Because the instructions are wider, they reduce the total number of +global load/store instructions in the program as well as some of the integer arithmetic associated +with calculating address offsets. Provided that the occupancy drops by a factor less than the vector +size and that there is no register spillage, this optimization increases the number of memory +instructions in flight, which is key to saturating the memory bandwidth. + +For this to work in our examples, the leading dimension `nx` must be a +multiple of the vector sizes 1, 2, or 4 (corresponding to `float`, `float2`, +or `float4`, respectively). + +First, we begin by introducing some preprocessor headers: + +```c++ +// Vectorized floats +#ifndef VEC_EXP +#define VEC_EXP 0 +#endif +#define VEC_LEN (1 << (VEC_EXP)) +using vec = __attribute__((__vector_size__(VEC_LEN * sizeof(float)))) float; +``` + +The user will pass in a compiler flag `-DVEC_EXP` with either 0 (no packed math), +1 (`float2`), or 2 (`float4`). The fundamental design of our stencil code is that +the normal `float` arrays are still be passed into the HIP kernels but within the kernels +we introduce new pointers to recast `float *` into the newly defined `vec`. +Next, we introduce some additional preprocessor headers +needed for the x-direction HIP kernels: + +```c++ +// x window stencil +#if VEC_LEN == 1 +#define XREG RADIUS +#define XREG_VEC RADIUS +#elif VEC_LEN == 2 +#if RADIUS > 2 +#define XREG 4 +#define XREG_VEC 2 +#else +#define XREG 2 +#define XREG_VEC 1 +#endif +#else +#define XREG VEC_LEN +#define XREG_VEC 1 +#endif +#define XREG_OFF (XREG-RADIUS) +``` + +The vectorized floats need to process adjacent and aligned values from the input buffer, `p_in`. +For example, when `VEC_LEN == 2` i.e., `float2`, each thread in the x-direction kernel +computes stencils for 2 grid points. Likewise, when `VEC_LEN == 4` i.e., `float4`, each +thread in the x-direction kernel computes stencils for 4 grid points. + +Consider the for loop inside the baseline x-direction kernel: + +```c++ + + // Compute the finite difference approximation + float out = 0.0f; + for (int r = 0; r <= 2 * R; ++r) { + out += p_in[0] * d_dz[r]; + p_in += 1; + } +``` + +This code example needs to be rewritten to accommodate for vectorized load and store instructions: + +```c++ + const vec *p_in_vec = reinterpret_cast(p_in); + vec *p_out_vec = reinterpret_cast(p_out); + float x_reg[2 * XREG + VEC_LEN] = {0.0f}; + vec *x_reg_vec = reinterpret_cast(x_reg); + + // Read x into registers + for (int r = 0; r < 2 * XREG_VEC + 1; ++r) + x_reg_vec[r] = p_in_vec[0 - XREG_VEC + r]; + + // Compute the finite difference approximation + vec out = {0.0f}; + for (int r = 0; r <= 2 * R; ++r) { + for (int ii = 0; ii < VEC_LEN; ++ii) + out[ii] += x_reg[XREG_OFF + r + ii] * d_dx[r]; + } +``` + +Several code changes have been applied: + +1. Recast all the `float *` buffers to the newly defined vectorized `vec *` +2. Introduce a register `x_reg` similar to the sliding window concept +introduced in the previous post. This `x_reg` register contains 9 elements when +`R == 4, VEC_LEN == 1` but will contain 10 and 12 elements when `VEC_LEN == 2` +and `VEC_LEN == 4`, respectively. Likewise, the `x_reg_vec` register contains +9, 5, and 3 elements when `VEC_LEN == 1`, `VEC_LEN == 2`, and `VEC_LEN == 4`, +respectively +3. Split the for loop into two. The first loop simply loads the vectorized floats +into `x_reg_vec` +4. The second loop is a double nested loop where `x_reg` and `d_dx` are shifted +to compute the finite difference for each of the `VEC_LEN` grid points. + +Below is a pictorial description of how the above definitions fit into the overall +vectorization: + + + +

+Figure 1: This figure illustrates how vectorized loads and stores affect the number +of stencil points computed for a thread. Each thread performs the same operation that requires +reading multiple values from data stored in registers and computes the stencil formula for multiple +outputs, determined by the vector length, `VEC_LEN`. The arrows pointing into the register array +show global load instructions and the arrows pointing away from the register array show global store +instructions. This implementation therefore relies on the L1 cache to efficiently re-use many of the +requested stencil neighbors. +

+ +Another significant change is the kernel launch configuration: + +```c++ +#define BLOCK_DIM_X (64 * (4 / RADIUS)) +#define BLOCK_DIM_Y RADIUS +``` + +Previously, the stencil kernels were launched with a thread block configuration of 256 x 1. +Now, the thread block configuration is selected based on the order of the finite difference +approximation. So if `R=4`, then the kernel has a thread block configuration of 64 x 4. + +The full code with launch parameters is: + +```c++ +template +__launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y)) +__global__ void compute_fd_x_vec_kernel(float *__restrict__ p_out, const float *__restrict__ p_in, + int line, int slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int i = x0 + VEC_LEN * (threadIdx.x + blockIdx.x * blockDim.x); + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + + if (i >= x1 || j >= y1 || k >= z1) return; + + size_t pos = i + line * j + slice * k; + + // Shift pointers such that that p_in points to the first value in the stencil + p_in += pos; + p_out += pos; + + const vec *p_in_vec = reinterpret_cast(p_in); + vec *p_out_vec = reinterpret_cast(p_out); + float x_reg[2 * XREG + VEC_LEN] = {0.0f}; + vec *x_reg_vec = reinterpret_cast(x_reg); + + // Read x into registers + for (int r = 0; r < 2 * XREG_VEC + 1; ++r) + x_reg_vec[r] = p_in_vec[0 - XREG_VEC + r]; + + // Compute the finite difference approximation + vec out = {0.0f}; + for (int r = 0; r <= 2 * R; ++r) { + for (int ii = 0; ii < VEC_LEN; ++ii) + out[ii] += x_reg[XREG_OFF + r + ii] * d_dx[r]; + } + + // Write the result + p_out_vec[0] = out; + +} + +template +void compute_fd_x_vec(float *p_out, const float *p_in, const float *d, int line, int + slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + dim3 block (BLOCK_DIM_X, BLOCK_DIM_Y); + dim3 grid; + grid.x = ceil(x1 - x0, VEC_LEN * block.x); + grid.y = ceil(y1 - y0, block.y); + grid.z = ceil(z1 - z0, block.z); + + compute_fd_x_vec_kernel<<>>(p_out, p_in, d, line, slice, x0, x1, y0, y1, z0, + z1); + HIP_CHECK(hipGetLastError()); + +} +``` + +The code transformation to vectorize the y-direction kernel is simpler: + +```c++ +template +__launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y)) +__global__ void compute_fd_y_vec_kernel(float *__restrict__ p_out, const float *__restrict__ p_in, + int line, int slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int i = x0 + VEC_LEN * (threadIdx.x + blockIdx.x * blockDim.x); + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + + if (i >= x1 || j >= y1 || k >= z1) return; + + size_t pos = i + line * j + slice * k; + size_t line_vec = line >> VEC_EXP; + + // Shift pointers such that that p_in points to the first value in the stencil + p_in += pos - R * line; + p_out += pos; + + const vec *p_in_vec = reinterpret_cast(p_in); + vec *p_out_vec = reinterpret_cast(p_out); + + // Compute the finite difference approximation + vec out = {0.0f}; + for (int r = 0; r <= 2 * R; ++r) { + out += p_in_vec[0] * d_dy[r]; + p_in_vec += line_vec; + } + + // Write the result + p_out_vec[0] = out; +} +``` + +Similar to the x-direction kernel, each thread outputs `VEC_LEN` elements in the x-direction +However, when accessing the data to load, it is being loaded from a vectorized type while striding +in the y-direction. Therefore, the stride needs to be modified based on +the vector length, `VEC_LEN`. This kernel uses the same thread block configuration as before. + +Below are the memory bandwidth numbers: + +|Kernel |Effective memory bandwidth | Achieved memory bandwidth | +|---|---|---| +| x-direction: Baseline | 990 GB/s | 1018 GB/s | +| x-direction: `VEC_LEN=1` | 980 GB/s | 1007 GB/s | +| x-direction: `VEC_LEN=2` | 1216 GB/s | 1256 GB/s | +| x-direction: `VEC_LEN=4` | 1240 GB/s | 1280 GB/s | +| y-direction: Baseline | 966 GB/s | 970 GB/s | +| y-direction: `VEC_LEN=1` | 967 GB/s | 968 GB/s | +| y-direction: `VEC_LEN=2` | 831 GB/s | 834 GB/s | +| y-direction: `VEC_LEN=4` | 1163 GB/s | 1172 GB/s | + +A few observations here. First, the baseline and `VEC_LEN=1` kernels +perform similarly which is expected since both operate on `float` arrays. +Secondly, all the kernels benefit from packed FP32 operations. +When `VEC_LEN=2`, both the effective and achieved memory bandwidths +are very high for the x-direction kernel. The y-direction kernel has +some mixed results depending on the `VEC_LEN`, but when `VEC_LEN=4`, +the kernel also performs well. Let us now dive a little deeper into +the memory level traffic: + +|Kernel|L1|L2 read|L2 write|HBM| +|---|---|---|---|---| +| x-direction: Baseline | 6979 MB | 604 MB | 537 MB | 1105 MB | +| x-direction: `VEC_LEN=1` | 6979 MB | 805 MB | 537 MB | 1105 MB | +| x-direction: `VEC_LEN=2` | 5906 MB | 672 MB | 537 MB | 1105 MB | +| x-direction: `VEC_LEN=4` | 3221 MB | 604 MB | 537 MB | 1105 MB | +| y-direction: Baseline | 5369 MB | 1610 MB | 537 MB | 1080 MB | +| y-direction: `VEC_LEN=1` | 5369 MB | 1610 MB | 537 MB | 1080 MB | +| y-direction: `VEC_LEN=2` | 10737 MB | 1611 MB | 537 MB | 1080 MB | +| y-direction: `VEC_LEN=4` | 5369 MB | 1758 MB | 537 MB | 1080 MB | + +For the x-direction kernels, packing the FP32 operations and data movement +reduces the amount of L1 traffic. In the case where `VEC_LEN=2`, the L1 traffic +nearly doubled, suggesting that there is a lack of coalescing. The y-direction kernel, +even with `VEC_LEN=4`, is slightly behind the corresponding x-direction kernel, but experiences high levels of L1 traffic. +Let us now consider a second optimization targeting the y-direction. + +## Optimization 2 - Local Data Share (LDS) + +The Local Data Share (LDS) is a fast on-CU user-programmable cache that can be +used to efficiently share data between all threads in a thread block. As discussed +in the [Register Pressure](https://rocm.blogs.amd.com/software-tools-optimization/register-pressure/README.html) blog post, +LDS is one of several memory resources shared by all threads in a thread block. +Each CU on a MI200 GPU has 64 KiB of LDS capacity. Since all active thread blocks +in a CU share the LDS resource, occupancy may drop if they each require too much LDS. +However, even if the occupancy drops, the performance of the kernel may still improve because LDS +instructions can replace global memory instructions that need to move data through the caches, and potentially HBM. + +Although the HBM traffic is already at expected levels, leveraging LDS for this particular +kernel alleviates the L1 cache pressure. Below is the modified code applying both +vectorized load and store instructions and LDS: + +```c++ +template +__launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y)) +__global__ void compute_fd_y_vec_kernel(float *__restrict__ p_out, const float *__restrict__ p_in, + int line, int slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int i = x0 + VEC_LEN * (threadIdx.x + blockIdx.x * blockDim.x); + const int j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + + size_t pos = i + line * j + slice * k; + size_t spos = threadIdx.x + (y0 + threadIdx.y) * BLOCK_DIM_X; + size_t line_vec = line >> VEC_EXP; + + // Shift pointers such that that p_in points to the first value in the stencil + p_in += pos; + p_out += pos; + + const vec *p_in_vec = reinterpret_cast(p_in); + vec *p_out_vec = reinterpret_cast(p_out); + + const int lds_y = BLOCK_DIM_Y + 2 * R; + __shared__ vec smem[BLOCK_DIM_X * lds_y]; + + // Read y into LDS + smem[spos - (BLOCK_DIM_X * R) ] = p_in_vec[0 - R * line_vec]; + smem[spos ] = p_in_vec[0]; + smem[spos + (BLOCK_DIM_X * BLOCK_DIM_Y)] = p_in_vec[0 + line_vec * BLOCK_DIM_Y]; + __syncthreads(); + + if (i >= x1 || j >= y1 || k >= z1) return; + + // Compute the finite difference approximation + vec out = {0.0f}; + for (int r = 0; r <= 2 * R; ++r) { + out += smem[spos + (r - R) * BLOCK_DIM_X] * d_dy[r]; + } + + // Write the result + p_out_vec[0] = out; +} +``` + +The code example above introduces the following: + +1. A new register `spos` that tracks the thread indexing in the LDS memory +2. A static LDS memory allocation, `smem`, that holds `vec` types with size `BLOCK_DIM_X * (BLOCK_DIM_Y + 2 * R)` +3. Reads `p_in_vec` into `smem` in a cyclic manner +4. Computes and stores the finite difference stencil using data loaded into the LDS array `smem` + +Before, we saw that `VEC_LEN=4` performed the best and therefore we revisit this choice for the LDS +implementation. Passing `-Rpass-analysis=kernel-resource-usage` to the compilation flag quickly lets us inspect the kernel +resources and the impact of adding LDS: + +```bash +remark: ./compute_fd_y_vec.hpp:13:0: SGPRs: 44 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: VGPRs: 39 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: AGPRs: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: ScratchSize [bytes/lane]: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: Occupancy [waves/SIMD]: 8 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: SGPRs Spill: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: VGPRs Spill: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_vec.hpp:13:0: LDS Size [bytes/block]: 0 [-Rpass-analysis=kernel-resource-usage] + +... + +remark: ./compute_fd_y_lds_vec.hpp:13:0: Function Name: _Z27compute_fd_y_lds_vec_kernelILi4EEvPfPKfS2_iiiiiiii [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: SGPRs: 24 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: VGPRs: 21 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: AGPRs: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: ScratchSize [bytes/lane]: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: Occupancy [waves/SIMD]: 5 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: SGPRs Spill: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: VGPRs Spill: 0 [-Rpass-analysis=kernel-resource-usage] +remark: ./compute_fd_y_lds_vec.hpp:13:0: LDS Size [bytes/block]: 12288 [-Rpass-analysis=kernel-resource-usage] +``` + +The LDS implementation with `VEC_LEN=4` requires 12288 bytes per block for a thread block size of 256 (1 wave / SIMD). Despite lowering +both the SGPR and VGPR usage, the occupancy drops to 5 due to the LDS usage: `12.288 KB x 5 = 61.44 KB < 64 KiB`. +The table below shows the performance. + +|Kernel |Effective memory bandwidth | Achieved memory bandwidth | +|---|---|---| +| y-direction: `VEC_LEN=4` | 1163 GB/s | 1172 GB/s | +| y-direction: `VEC_LEN=4` + LDS| 1272 GB/s | 1289 GB/s | + +Despite a slightly lower occupancy for the kernel with LDS, there is significant improvement in the effective and achieved memory bandwidth compared to the kernel without LDS. In fact, +this performance is nearly on par with the BabelStream performance discussed earlier. +Next, we investigate the memory traffic: + +|Kernel|L1|L2 read|L2 write|HBM| LDS Instructions / wave | +|---|---|---|---|---|---| +| y-direction: `VEC_LEN=4` | 5369 MB | 1758 MB | 537 MB | 1080 MB | 0.0 | +| y-direction: `VEC_LEN=4` + LDS | 2147 MB | 1611 MB | 537 MB | 1080 MB | 12.0 | + +The L1 traffic has dropped by more than a factor of two and there is a slight reduction +of traffic in the L2 reads. According to `rocprof`, the number of LDS instructions +per wave increased from 0 to 12 - this corresponds to 3 instructions reading from HBM +and 9 instructions computing and storing the finite difference into the `out` register. + +All three directional kernels (x, y, and z) obtain acceptable performance on a single MI250X GCD. +The next section explores kernel fusion to combine all three individual directional stencil +kernels into one monolithic kernel to obtain further speedups. + +## Kernel fusion + +Now that all three directional kernels are highly optimized, the next +task is to combine them into a single kernel to further reduce data movement. +One of the challenges with applying kernel fusion is that it often stresses +the available hardware resources like registers and LDS. As a result, +it may be necessary to reduce the tile size and or occupancy. In this case, we +will see that we can maintain the same tile size as before. First, by applying vectorization and LDS, we combine +the x-direction and y-direction kernels: + +```c++ +template +__launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y)) +__global__ void compute_fd_xy_lds_vec_kernel(float *p_out, const float *p_in, const float *d, int line, int + slice, int x0, int x1, int y0, int y1, int z0, int z1) { + + const int sj = y0 + threadIdx.y; + const int lds_y = BLOCK_DIM_Y + 2*R; + const int i = x0 + VEC_LEN*(threadIdx.x + blockIdx.x * blockDim.x); + const int j = sj + blockIdx.y * blockDim.y; + const int k = z0 + threadIdx.z + blockIdx.z * blockDim.z; + size_t pos = i + line * j + slice * k; + size_t spos = threadIdx.x + sj * BLOCK_DIM_X; + size_t line_vec = line >> VEC_EXP; + + p_in += pos; + p_out += pos; + float x_reg[2 * XREG + VEC_LEN] = {0.0f}; + __shared__ vec smem[BLOCK_DIM_X * lds_y]; + + // Recast as vectorized floats + const vec *p_in_vec = reinterpret_cast(p_in); + vec *p_out_vec = reinterpret_cast(p_out); + vec *x_reg_vec = reinterpret_cast(x_reg); + + // Read x into registers + for (int r = 0; r < 2*XREG_VEC+1; ++r) + x_reg_vec[r] = p_in_vec[0 - XREG_VEC + r]; + + // Read y into LDS + smem[spos] = x_reg_vec[XREG_VEC]; + smem[spos - (BLOCK_DIM_X * R)] = p_in_vec[0 - R*line_vec]; + smem[spos + BLOCK_DIM_X * BLOCK_DIM_Y] = p_in_vec[0 + line_vec * BLOCK_DIM_Y]; + __syncthreads(); + + if (i >= x1 || j >= y1 || k >= z1) return; + + // Compute the finite difference approximation in the xy-direction + vec out = {0.0f}; + for (int r = 0; r <= 2 * R; ++r) { + out += smem[spos + (r - R) * BLOCK_DIM_X] * d_dy[r]; + for (int ii = 0; ii < VEC_LEN; ++ii) + out[ii] += x_reg[XREG_OFF + r + ii] * d_dx[r]; + } + + __builtin_nontemporal_store(out,&p_out_vec[0]); + +} +``` + +Also note that we are introducing nontemporal stores via the intrinsic `__builtin_nontemporal_store`, see +[Finite Difference Laplacian Part 3](https://rocm.blogs.amd.com/high-performance-computing/finite-difference/laplacian-part3/README.html#nontemporal-memory-access) +for more details. Below are the performance numbers in comparison with the single direction kernels: + +|Kernel |Effective memory bandwidth | Achieved memory bandwidth | +|---|---|---| +| x-direction: `VEC_LEN=4` | 1240 GB/s | 1280 GB/s | +| y-direction: `VEC_LEN=4` + LDS | 1272 GB/s | 1289 GB/s | +| xy-direction: `VEC_LEN=4` + LDS| 1252 GB/s | 1292 GB/s | + +The xy-direction kernel itself is comparable to the x-direction and y-direction kernels. +One can expect up to a 2x in savings in data movement from this optimization. The next +challenge is to combine this fused kernel with z-direction kernel that uses the +sliding window technique. + +```c++ +template +__launch_bounds__((BLOCK_DIM_X) * (BLOCK_DIM_Y)) +__global__ void compute_fd_xyz_lds_window_vec_kernel(float *p_out, const float *p_in, int line, int + slice, int x0, int x1, int y0, int y1, int z0, int z1, int nw) { + + const size_t i = (x0 + VEC_LEN * (threadIdx.x + blockIdx.x * blockDim.x)); + const size_t j = y0 + threadIdx.y + blockIdx.y * blockDim.y; + + if (i >= x1) return; + + // Determine the k indices covered by this sliding window + // The extent cannot exceed the z1 + const int kbegin = z0 + blockIdx.z * nw; + const int kend = kbegin + nw > z1 ? z1 : kbegin + nw; + + size_t pos = i + line * j + slice * kbegin; + size_t slice_vec = slice >> VEC_EXP; + size_t line_vec = line >> VEC_EXP; + + // Shift pointers such that that p_in points to the first value in the sliding window + p_in += pos - R * slice; + p_out += pos; + const vec *p_in_vec = reinterpret_cast(p_in); + vec *p_out_vec = reinterpret_cast(p_out); + + // LDS for y direction + const int lds_y = BLOCK_DIM_Y + 2*R; + const int sj = y0 + threadIdx.y; + size_t spos = threadIdx.x + sj * BLOCK_DIM_X; + __shared__ vec smem[BLOCK_DIM_X * lds_y]; + + // z direction sliding window + vec w[2 * R + 1]; + + // solution register + vec out[R+1]; + + // x direction stencil + float x_reg[2 * XREG + VEC_LEN]; + vec *x_reg_vec = reinterpret_cast(x_reg); + + // 1. Prime the z sliding window + for (int r = 0; r < R; ++r) { + w[r] = p_in_vec[0]; + p_in_vec += slice_vec; + } + for (int r = R; r < 2 * R; ++r) { + + // 2. Load x into registers + for (int r2 = 0; r2 < 2*XREG_VEC + 1; ++r2) + x_reg_vec[r2] = p_in_vec[0 - XREG_VEC + r2]; + + // 3. Load y into LDS + __syncthreads(); + { + smem[spos - (BLOCK_DIM_X * R)] = p_in_vec[0 - R * line_vec]; + smem[spos] = x_reg_vec[XREG_VEC]; + smem[spos + (BLOCK_DIM_X * BLOCK_DIM_Y)] = p_in_vec[0 + line_vec * BLOCK_DIM_Y]; + } + __syncthreads(); + + // 4. Compute xy stencils + out[r-R] = {0.0f}; + for (int r2 = 0; r2 <= 2 * R; ++r2) { + out[r-R] += smem[spos + (r2 - R) * BLOCK_DIM_X] * d_dy[r2]; // y-direction + for (int ii = 0; ii < VEC_LEN; ++ii) + out[r-R][ii] += x_reg[XREG_OFF + r2 + ii] * d_dx[r2]; // x-direction + } + + // Prime the z sliding window + w[r] = x_reg_vec[XREG_VEC]; + p_in_vec += slice_vec; + } + + // Apply the sliding window along the given grid direction + for (int k = kbegin; k < kend; ++k) { + + // 2. Load x into registers + for (int r2 = 0; r2 < 2*XREG_VEC+1; ++r2) + x_reg_vec[r2] = p_in_vec[0 - XREG_VEC + r2]; // x - R + + // 3. Load y into LDS + __syncthreads(); + { + smem[spos - (BLOCK_DIM_X * R)] = p_in_vec[0 - R * line_vec]; // y - R + smem[spos] = x_reg_vec[XREG_VEC]; + smem[spos + (BLOCK_DIM_X * BLOCK_DIM_Y)] = p_in_vec[0 + line_vec * BLOCK_DIM_Y]; // y + R + } + __syncthreads(); + + // 4. Compute xyz stencils + w[2*R] = x_reg_vec[XREG_VEC]; + out[R] = {0.0f}; + for (int r = 0; r <= 2 * R; ++r) { + out[0] += w[r] * d_dz[r]; // z-direction + out[R] += smem[spos + (r - R) * BLOCK_DIM_X] * d_dy[r]; // y-direction + for (int ii = 0; ii < VEC_LEN; ++ii) + out[R][ii] += x_reg[XREG_OFF + r + ii] * d_dx[r]; // x-direction + } + + // 5. Write only if within y boundary + if (j < y1) + __builtin_nontemporal_store(out[0],&p_out_vec[0]); + + // 6. Update the sliding window by shifting it forward one step + for (int r = 0; r < R; ++r) + out[r] = out[r+1]; + for (int r = 0; r < 2*R; ++r) + w[r] = w[r+1]; + + // Increment pointers + p_in_vec += slice_vec; + p_out_vec += slice_vec; + } +} +``` + +For this final monolithic kernel, we summarize few key ingredients below. + +1. Exit if the threads exceeds `x1` only +2. Split the priming step into two parts +3. First part loads the z-direction stencil into a sliding window register `w` +4. Second part still loads the z-direction stencil but also computes the x and y direction stencils and stores the result into a temporary output register `out` +5. During the sliding window phase, the z-direction stencil computes and combines with the previously store xy-direction stencil. +6. Introduce additional `__syncthreads()` before the LDS load operations to avoid any data hazards +7. Write the result only if the thread does not exceed `y1` + +Below is the result across various values of `nw`: + + + +

+Figure 1: The fully combined xyz kernel reach over 1000 GB/s in both the achieved +and effective memory bandwidths. The R/W ratio drops and approaches one as the window +size increases. +

+ +At around `nw = 100` and `nw = 200`, both memory bandwidth FOMs hit just over 1000 GB/s. +It should also be noted that as `nw` increases, the R/W hovers slightly above 1 and +is worse than the predicted value calculated from [Part 2](./seismic-stencils-part2.md). +Another interesting observation, unlike in the z-direction sliding window kernel, is that +both the achieved and memory bandwidths are relatively lower when `nw` is either too +small or too large. + +Even the optimal range of numbers still fall short of the 1200 GB/s observed +from the individual directional kernels. However, executing the fused xyz-kernel +is still faster than executing the three individual optimized kernels or the xy-direction +and z-direction sliding window kernels sequentially. + +We can approximate the speedup with these formulas: + +$$ + T_\mathrm{xyz} = \frac{N}{1000 \mathrm{GB/s}}, + T_\mathrm{xy} = \frac{N}{1252 \mathrm{GB/s}}, + T_\mathrm{x} = \frac{N}{1240 \mathrm{GB/s}}, + T_\mathrm{y} = \frac{N}{1272 \mathrm{GB/s}}, + T_\mathrm{z} = \frac{N}{1200 \mathrm{GB/s}} +$$ + +Where $T$ represents the kernel execution time and $N$ represents the size of the cube. The +speedup one can achieve over executing the three individual kernels is approximated using +the following formula: + +$$ + \frac{T_\mathrm{x}+T_\mathrm{y}+T_\mathrm{z}}{T_\mathrm{xyz}} = \frac{1000}{1240}+\frac{1000}{1272}+\frac{1000}{1200} = 2.42\\ +$$ + +Likewise, if we wished to combine only the xy-direction kernel, the speedup is: + +$$ + \frac{T_\mathrm{xy}+T_\mathrm{z}}{T_\mathrm{xyz}} = \frac{1000}{1252}+\frac{1000}{1200} = 1.63 +$$ + +Even with this initial attempt at combining the three kernels into a *single pass approach*, +it still offers up to a 1.63x - 2.42x speedup. + +## Summary and next steps + +In these last three blog posts, we have covered a basic HIP implementation of computing +seismic stencils with high order finite difference computations. Using the same performance +metrics as the [Finite Difference Laplacian series](../../finite-difference/docs/Laplacian_Part1.md), +we developed a methodology to approximate the effective memory bandwidth and compared it against +the achieved or actual memory bandwidth. These posts focused on the following optimization strategies. + +1. *Aligned memory*: this optimization uses padded memory allocations so that the leading dimension is some multiple +of the GPU cache line size. +2. *Sliding window*: this technique holds onto a local volume of the input array data in registers +and compute the stencil in the z-direction entirely using these registers. This "window" helps eliminate +redundant global memory fetches as the kernel iterates through xy-planes +3. *Vectorization*: recast our `float` device buffers as `float2` or `float4` buffers. This technique +increases the number of bytes in flight and reduces the number of global load/store instructions +4. *Local Data Share (LDS)*: utilization of the LDS to store the grid data and compute the stencil in the y-direction +reduces pressure on global memory (caches and HBM). +While storing all the grid data in LDS instead of in registers may help reduce register pressure, allocating +too much LDS per thread block lowers the occupancy. + +All four optimizations result in significant performance boosts for the individual directional kernels. +Furthermore, combining the x and y kernels with the above optimizations gives near identical performance +to the x-direction and y-direction kernels. The final optimization fused all three stencil kernels +into a single one. The end result is a *one-pass* approach yielding nearly a 2.5x speedup over the *three-pass* approach. + +In the next blog post, we extend this effort to even higher order finite difference stencils, i.e., beyond `R=4`, +and study the performance across different grid sizes and hardware architecture. If you have any questions, +please do not hesitate to reach out to us on [Github Discussions](https://github.com/ROCm/rocm-blogs/discussions). + +[Accompanying code examples](https://github.com/amd/HPCTrainingExamples/tree/main/rocm-blogs-codes/seismic-stencils) + +[^1]:Testing conducted using ROCm version 6.1.0-82. Benchmark results are not +validated performance numbers, and are provided only to demonstrate relative +performance improvements of code modifications. Actual performance results +depend on multiple factors including system configuration and environment +settings, reproducibility of the results is not guaranteed. + +[^2]:[BabelStream case studies](https://www.olcf.ornl.gov/wp-content/uploads/2-16-23-node_performance.pdf)