[Feature request]: Dither PWM

[Peter-van-Tol]

Initial Checks

• I have searched Google & GitHub for similar requests and couldn't find anything
• I have read the documentation and couldn't find anything

Description

Currently the resolution of PWM is limited to the number of cycles within a PWM period. For example, when the FPGA runs on 40 MHz and a PWM frequency of 1 kHZ is requested, the resolution of the PWM is 40,000. This effect is worse on higher PWM frequencies.

One solution is to switch to PDM, which is already supported. However this mode does not have a fixed frequency and might not be supported by PWM to voltage converters.

The other solution is to implement dithering, allowing for full 32-bit resolution, regardless of the frequency. Proposed communication to PWM:

• byte 0: pick-off (position of the decimal point);
• byte 1-3: frequency in cycles;
• byte 4-7: duty-cycle.

The counter for the duty cycle will be enlarged to 64-bit, fixed point (32 bit - 32 bit). At every start of a PWM cycle, this counter is increased with the value of duty-cycle (bytes 4-7), rigth-shifted with the pick-off (byte 0).

Every clock-cycle the counter of the duty-cycle will be reduced with 1.0 (0x0000000100000000). When the value of the counter is below 1.0, the output pin will be switched off until the end of the PWM cycle.

This method ensures that changing the frequency does not influence the duty-cycle counter.

Affected Components

• CLI.
• Supported boards (i.e. 5A-75B, 5A-75E, HUB75HAT, etc.)
• Supported connections (i.e. SPI, Ethernet, etc.)
• Modules (i.e. GPIO, PWM, stepgen, encoders, etc.)
• Documentation