From f61de5007b2ad494d322c68804eee646928b8521 Mon Sep 17 00:00:00 2001 From: cchr Date: Mon, 9 Sep 2024 13:21:06 +0200 Subject: [PATCH] Introduce separate CMD_IN state --- fpga-arch/bsv/SWD.bsv | 7 +- fpga-arch/swd_module.v | 350 +++++++++++++++++++++-------------------- 2 files changed, 180 insertions(+), 177 deletions(-) diff --git a/fpga-arch/bsv/SWD.bsv b/fpga-arch/bsv/SWD.bsv index 3063910..bdcb5c8 100644 --- a/fpga-arch/bsv/SWD.bsv +++ b/fpga-arch/bsv/SWD.bsv @@ -58,6 +58,7 @@ typedef struct { typedef enum { IDLE, + CMD_IN, RESET, RW } State deriving (Eq, Bits); @@ -97,6 +98,7 @@ module swd_module (ScaffoldSWDModule); bus_reg_status <= {pack(state == IDLE), 5'b0, pack(status)}; endrule + // Only register writes if we are currently idling rule do_bus_write ((bus_write == 1) && (state == IDLE)); if (bus_en_wdata == 1) begin wdata <= shiftInAt0(wdata, bus_write_data); @@ -104,6 +106,7 @@ module swd_module (ScaffoldSWDModule); if (bus_en_cmd == 1) begin cmd <= tagged Valid(unpack(bus_write_data)); + state <= CMD_IN; end endrule @@ -111,9 +114,7 @@ module swd_module (ScaffoldSWDModule); ready <= swd_controller.ready; endrule - // ONLY do something if there is a valid command registered, and if - // the user is not currently writing to some register. - rule do_idle ((state == IDLE) && (bus_write == 0) && isValid(cmd)); + rule do_cmd ((state == CMD_IN) && isValid(cmd)); let new_cmd = fromMaybe(?, cmd); if (new_cmd.reset == 1) begin diff --git a/fpga-arch/swd_module.v b/fpga-arch/swd_module.v index 90ae02e..f6512cb 100644 --- a/fpga-arch/swd_module.v +++ b/fpga-arch/swd_module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2024.01-9-gc481d7f5 (build c481d7f5) // -// On Thu Sep 5 16:29:16 CEST 2024 +// On Mon Sep 9 13:18:32 CEST 2024 // // // Ports: @@ -24,8 +24,7 @@ // en_status I 1 // swd_in I 1 // -// Combinational paths from inputs to outputs: -// write -> trigger +// No combinational paths from inputs to outputs // // @@ -229,7 +228,7 @@ module swd_module(CLK, // rule scheduling signals wire WILL_FIRE_RL_do_bus_read_rdata, WILL_FIRE_RL_do_bus_write, - WILL_FIRE_RL_do_idle, + WILL_FIRE_RL_do_cmd, WILL_FIRE_RL_do_reset, WILL_FIRE_RL_do_rw; @@ -249,7 +248,7 @@ module swd_module(CLK, wire [3 : 0] MUX_swd_controller_state$write_1__VAL_1, MUX_swd_controller_state$write_1__VAL_3, MUX_swd_controller_state$write_1__VAL_7; - wire [1 : 0] MUX_state$write_1__VAL_2; + wire [1 : 0] MUX_state$write_1__VAL_3; wire MUX_cmd$write_1__SEL_1, MUX_state$write_1__SEL_1, MUX_swd_controller_cnt$write_1__PSEL_1, @@ -282,77 +281,77 @@ module swd_module(CLK, // remaining internal signals wire [15 : 0] _0xE79E__q2; - wire [6 : 0] i__h1365, x__h14825; + wire [6 : 0] i__h1457, x__h15006; wire [1 : 0] cmd_BITS_1_TO_0__q1; wire swd_controller_cnt_2_ULE_8___d35, - swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301, - x__h1346, - x__h20049, - x__h20062, - x__h20064, - x__h21248, - x__h21261, - z__h24495, - z__h24502, - z__h24509, - z__h24516, - z__h24523, - z__h24530, - z__h24537, - z__h24544, - z__h24551, - z__h24558, - z__h24565, - z__h24572, - z__h24579, - z__h24586, - z__h24593, - z__h24600, - z__h24607, - z__h24614, - z__h24621, - z__h24628, - z__h24635, - z__h24642, - z__h24649, - z__h24656, - z__h24663, - z__h24670, - z__h24677, - z__h24684, - z__h24691, - z__h24698, - z__h35143, - z__h35150, - z__h35157, - z__h35164, - z__h35171, - z__h35178, - z__h35185, - z__h35192, - z__h35199, - z__h35206, - z__h35213, - z__h35220, - z__h35227, - z__h35234, - z__h35241, - z__h35248, - z__h35255, - z__h35262, - z__h35269, - z__h35276, - z__h35283, - z__h35290, - z__h35297, - z__h35304, - z__h35311, - z__h35318, - z__h35325, - z__h35332, - z__h35339, - z__h35346, - z__h35353; + swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d298, + x__h1438, + x__h20247, + x__h20260, + x__h20262, + x__h21446, + x__h21459, + z__h24693, + z__h24700, + z__h24707, + z__h24714, + z__h24721, + z__h24728, + z__h24735, + z__h24742, + z__h24749, + z__h24756, + z__h24763, + z__h24770, + z__h24777, + z__h24784, + z__h24791, + z__h24798, + z__h24805, + z__h24812, + z__h24819, + z__h24826, + z__h24833, + z__h24840, + z__h24847, + z__h24854, + z__h24861, + z__h24868, + z__h24875, + z__h24882, + z__h24889, + z__h24896, + z__h35341, + z__h35348, + z__h35355, + z__h35362, + z__h35369, + z__h35376, + z__h35383, + z__h35390, + z__h35397, + z__h35404, + z__h35411, + z__h35418, + z__h35425, + z__h35432, + z__h35439, + z__h35446, + z__h35453, + z__h35460, + z__h35467, + z__h35474, + z__h35481, + z__h35488, + z__h35495, + z__h35502, + z__h35509, + z__h35516, + z__h35523, + z__h35530, + z__h35537, + z__h35544, + z__h35551; // value method bus_reg_rdata assign reg_rdata = bus_reg_rdata ; @@ -370,7 +369,7 @@ module swd_module(CLK, assign out_en = swd_controller_out_en ; // value method trigger - assign trigger = WILL_FIRE_RL_do_idle && cmd[6] ; + assign trigger = WILL_FIRE_RL_do_cmd && cmd[6] ; // submodule swd_controller_prescaler_ctr Counter #(.width(32'd8), @@ -387,27 +386,26 @@ module swd_module(CLK, .Q_OUT(swd_controller_prescaler_ctr$Q_OUT)); // rule RL_do_bus_read_rdata - assign WILL_FIRE_RL_do_bus_read_rdata = read && en_rdata && state != 2'd2 ; + assign WILL_FIRE_RL_do_bus_read_rdata = read && en_rdata && state != 2'd3 ; // rule RL_do_bus_write assign WILL_FIRE_RL_do_bus_write = write && state == 2'd0 ; - // rule RL_do_idle - assign WILL_FIRE_RL_do_idle = + // rule RL_do_cmd + assign WILL_FIRE_RL_do_cmd = swd_controller_state == 4'd0 && !swd_controller_status[2] && - state == 2'd0 && - !write && + state == 2'd1 && cmd[8] ; // rule RL_do_reset assign WILL_FIRE_RL_do_reset = swd_controller_state == 4'd0 && !swd_controller_status[2] && - state == 2'd1 ; + state == 2'd2 ; // rule RL_do_rw assign WILL_FIRE_RL_do_rw = swd_controller_state == 4'd0 && swd_controller_status[2] && - state == 2'd2 ; + state == 2'd3 ; // inputs to muxes for submodule ports assign MUX_cmd$write_1__SEL_1 = WILL_FIRE_RL_do_bus_write && en_cmd ; @@ -448,9 +446,9 @@ module swd_module(CLK, swd_controller_state == 4'd6 && swd_controller_prescaler_ctr$Q_OUT == 8'd0 ; assign MUX_swd_controller_data$write_1__SEL_3 = - WILL_FIRE_RL_do_idle && !cmd[7] && !cmd[2] ; + WILL_FIRE_RL_do_cmd && !cmd[7] && !cmd[2] ; assign MUX_swd_controller_packet$write_1__SEL_2 = - WILL_FIRE_RL_do_idle && !cmd[7] ; + WILL_FIRE_RL_do_cmd && !cmd[7] ; assign MUX_swd_controller_packet$write_1__SEL_3 = swd_controller_state == 4'd1 && swd_controller_prescaler_ctr$Q_OUT == 8'd0 && @@ -499,33 +497,33 @@ module swd_module(CLK, assign MUX_rdata$write_1__VAL_1 = { 8'd0, rdata[31:8] } ; assign MUX_rdata$write_1__VAL_2 = swd_controller_rnw ? - (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301 ? + (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d298 ? 32'd0 : swd_controller_data[31:0]) : 32'd0 ; - assign MUX_state$write_1__VAL_2 = cmd[7] ? 2'd1 : 2'd2 ; + assign MUX_state$write_1__VAL_3 = cmd[7] ? 2'd2 : 2'd3 ; assign MUX_swd_controller_cnt$write_1__VAL_2 = (swd_controller_ack == 3'b100) ? 7'd33 : 7'd1 ; assign MUX_swd_controller_cnt$write_1__VAL_4 = swd_controller_request_in$whas ? 7'd10 : 7'd126 ; assign MUX_swd_controller_cnt$write_1__VAL_5 = (swd_controller_prescaler_ctr$Q_OUT == 8'd0) ? - x__h14825 : + x__h15006 : 7'd33 ; assign MUX_swd_controller_cnt$write_1__VAL_6 = - (swd_controller_prescaler_ctr$Q_OUT == 8'd0) ? x__h14825 : 7'd1 ; + (swd_controller_prescaler_ctr$Q_OUT == 8'd0) ? x__h15006 : 7'd1 ; assign MUX_swd_controller_data$write_1__VAL_1 = { swd_in, swd_controller_data[32:1] } ; assign MUX_swd_controller_data$write_1__VAL_2 = { 1'd0, swd_controller_data[32:1] } ; assign MUX_swd_controller_data$write_1__VAL_3 = - { z__h24698 ^ wdata[7], + { z__h24896 ^ wdata[7], wdata[7:0], wdata[15:8], wdata[23:16], wdata[31:24] } ; assign MUX_swd_controller_packet$write_1__VAL_2 = - { 1'd1, cmd[3:0], cmd[2] ? x__h20049 : x__h21248, 2'd1 } ; + { 1'd1, cmd[3:0], cmd[2] ? x__h20247 : x__h21446, 2'd1 } ; assign MUX_swd_controller_packet$write_1__VAL_3 = { swd_controller_packet[6:0], 1'd0 } ; assign MUX_swd_controller_state$write_1__VAL_1 = @@ -545,15 +543,15 @@ module swd_module(CLK, end assign MUX_swd_controller_swd_out$write_1__VAL_2 = swd_controller_cnt > 7'd71 || swd_controller_cnt <= 7'd55 || - x__h1346 ; + x__h1438 ; assign MUX_swd_controller_swd_out$write_1__VAL_3 = swd_controller_cnt_2_ULE_8___d35 && swd_controller_packet[7] ; // inlined wires assign swd_controller_request_in$whas = WILL_FIRE_RL_do_reset && ready || - WILL_FIRE_RL_do_idle && !cmd[7] ; - assign swd_controller_reset_in$whas = WILL_FIRE_RL_do_idle && cmd[7] ; + WILL_FIRE_RL_do_cmd && !cmd[7] ; + assign swd_controller_reset_in$whas = WILL_FIRE_RL_do_cmd && cmd[7] ; // register bus_reg_rdata assign bus_reg_rdata$D_IN = rdata[7:0] ; @@ -580,24 +578,28 @@ module swd_module(CLK, // register state always@(MUX_state$write_1__SEL_1 or - WILL_FIRE_RL_do_idle or - MUX_state$write_1__VAL_2 or WILL_FIRE_RL_do_rw) + MUX_cmd$write_1__SEL_1 or + WILL_FIRE_RL_do_cmd or + MUX_state$write_1__VAL_3 or WILL_FIRE_RL_do_rw) begin case (1'b1) // synopsys parallel_case - MUX_state$write_1__SEL_1: state$D_IN = 2'd2; - WILL_FIRE_RL_do_idle: state$D_IN = MUX_state$write_1__VAL_2; + MUX_state$write_1__SEL_1: state$D_IN = 2'd3; + MUX_cmd$write_1__SEL_1: state$D_IN = 2'd1; + WILL_FIRE_RL_do_cmd: state$D_IN = MUX_state$write_1__VAL_3; WILL_FIRE_RL_do_rw: state$D_IN = 2'd0; default: state$D_IN = 2'b10 /* unspecified value */ ; endcase end assign state$EN = - WILL_FIRE_RL_do_reset && ready || WILL_FIRE_RL_do_idle || + WILL_FIRE_RL_do_reset && ready || + WILL_FIRE_RL_do_bus_write && en_cmd || + WILL_FIRE_RL_do_cmd || WILL_FIRE_RL_do_rw ; // register status assign status$D_IN = swd_controller_rnw ? - (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301 ? + (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d298 ? 2'd3 : swd_controller_status[1:0]) : swd_controller_status[1:0] ; @@ -611,7 +613,7 @@ module swd_module(CLK, // register swd_controller_cnt always@(MUX_swd_controller_cnt$write_1__SEL_1 or - x__h14825 or + x__h15006 or MUX_swd_controller_cnt$write_1__SEL_2 or MUX_swd_controller_cnt$write_1__VAL_2 or MUX_swd_controller_cnt$write_1__SEL_3 or @@ -624,7 +626,7 @@ module swd_module(CLK, begin case (1'b1) // synopsys parallel_case MUX_swd_controller_cnt$write_1__SEL_1: - swd_controller_cnt$D_IN = x__h14825; + swd_controller_cnt$D_IN = x__h15006; MUX_swd_controller_cnt$write_1__SEL_2: swd_controller_cnt$D_IN = MUX_swd_controller_cnt$write_1__VAL_2; MUX_swd_controller_cnt$write_1__SEL_3: swd_controller_cnt$D_IN = 7'd3; @@ -679,7 +681,7 @@ module swd_module(CLK, swd_controller_prescaler_ctr$Q_OUT == 8'd0 || swd_controller_state == 4'd6 && swd_controller_prescaler_ctr$Q_OUT == 8'd0 || - WILL_FIRE_RL_do_idle && !cmd[7] && !cmd[2] || + WILL_FIRE_RL_do_cmd && !cmd[7] && !cmd[2] || WILL_FIRE_RL_do_rw ; // register swd_controller_out_en @@ -710,7 +712,7 @@ module swd_module(CLK, end assign swd_controller_packet$EN = WILL_FIRE_RL_do_reset && ready || - WILL_FIRE_RL_do_idle && !cmd[7] || + WILL_FIRE_RL_do_cmd && !cmd[7] || swd_controller_state == 4'd1 && swd_controller_prescaler_ctr$Q_OUT == 8'd0 && swd_controller_cnt_2_ULE_8___d35 || @@ -851,78 +853,78 @@ module swd_module(CLK, // remaining internal signals assign _0xE79E__q2 = 16'hE79E ; assign cmd_BITS_1_TO_0__q1 = cmd[1:0] ; - assign i__h1365 = 7'd71 - swd_controller_cnt ; + assign i__h1457 = 7'd71 - swd_controller_cnt ; assign swd_controller_cnt_2_ULE_8___d35 = swd_controller_cnt <= 7'd8 ; - assign swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301 = - z__h35353 ^ swd_controller_data[32] ; - assign x__h1346 = _0xE79E__q2[i__h1365[3:0]] ; - assign x__h14825 = swd_controller_cnt - 7'd1 ; - assign x__h20049 = x__h20062 ^ cmd_BITS_1_TO_0__q1[1] ; - assign x__h20062 = x__h20064 ^ cmd_BITS_1_TO_0__q1[0] ; - assign x__h20064 = ~cmd[3] ; - assign x__h21248 = x__h21261 ^ cmd_BITS_1_TO_0__q1[1] ; - assign x__h21261 = cmd[3] ^ cmd_BITS_1_TO_0__q1[0] ; - assign z__h24495 = wdata[24] ^ wdata[25] ; - assign z__h24502 = z__h24495 ^ wdata[26] ; - assign z__h24509 = z__h24502 ^ wdata[27] ; - assign z__h24516 = z__h24509 ^ wdata[28] ; - assign z__h24523 = z__h24516 ^ wdata[29] ; - assign z__h24530 = z__h24523 ^ wdata[30] ; - assign z__h24537 = z__h24530 ^ wdata[31] ; - assign z__h24544 = z__h24537 ^ wdata[16] ; - assign z__h24551 = z__h24544 ^ wdata[17] ; - assign z__h24558 = z__h24551 ^ wdata[18] ; - assign z__h24565 = z__h24558 ^ wdata[19] ; - assign z__h24572 = z__h24565 ^ wdata[20] ; - assign z__h24579 = z__h24572 ^ wdata[21] ; - assign z__h24586 = z__h24579 ^ wdata[22] ; - assign z__h24593 = z__h24586 ^ wdata[23] ; - assign z__h24600 = z__h24593 ^ wdata[8] ; - assign z__h24607 = z__h24600 ^ wdata[9] ; - assign z__h24614 = z__h24607 ^ wdata[10] ; - assign z__h24621 = z__h24614 ^ wdata[11] ; - assign z__h24628 = z__h24621 ^ wdata[12] ; - assign z__h24635 = z__h24628 ^ wdata[13] ; - assign z__h24642 = z__h24635 ^ wdata[14] ; - assign z__h24649 = z__h24642 ^ wdata[15] ; - assign z__h24656 = z__h24649 ^ wdata[0] ; - assign z__h24663 = z__h24656 ^ wdata[1] ; - assign z__h24670 = z__h24663 ^ wdata[2] ; - assign z__h24677 = z__h24670 ^ wdata[3] ; - assign z__h24684 = z__h24677 ^ wdata[4] ; - assign z__h24691 = z__h24684 ^ wdata[5] ; - assign z__h24698 = z__h24691 ^ wdata[6] ; - assign z__h35143 = swd_controller_data[0] ^ swd_controller_data[1] ; - assign z__h35150 = z__h35143 ^ swd_controller_data[2] ; - assign z__h35157 = z__h35150 ^ swd_controller_data[3] ; - assign z__h35164 = z__h35157 ^ swd_controller_data[4] ; - assign z__h35171 = z__h35164 ^ swd_controller_data[5] ; - assign z__h35178 = z__h35171 ^ swd_controller_data[6] ; - assign z__h35185 = z__h35178 ^ swd_controller_data[7] ; - assign z__h35192 = z__h35185 ^ swd_controller_data[8] ; - assign z__h35199 = z__h35192 ^ swd_controller_data[9] ; - assign z__h35206 = z__h35199 ^ swd_controller_data[10] ; - assign z__h35213 = z__h35206 ^ swd_controller_data[11] ; - assign z__h35220 = z__h35213 ^ swd_controller_data[12] ; - assign z__h35227 = z__h35220 ^ swd_controller_data[13] ; - assign z__h35234 = z__h35227 ^ swd_controller_data[14] ; - assign z__h35241 = z__h35234 ^ swd_controller_data[15] ; - assign z__h35248 = z__h35241 ^ swd_controller_data[16] ; - assign z__h35255 = z__h35248 ^ swd_controller_data[17] ; - assign z__h35262 = z__h35255 ^ swd_controller_data[18] ; - assign z__h35269 = z__h35262 ^ swd_controller_data[19] ; - assign z__h35276 = z__h35269 ^ swd_controller_data[20] ; - assign z__h35283 = z__h35276 ^ swd_controller_data[21] ; - assign z__h35290 = z__h35283 ^ swd_controller_data[22] ; - assign z__h35297 = z__h35290 ^ swd_controller_data[23] ; - assign z__h35304 = z__h35297 ^ swd_controller_data[24] ; - assign z__h35311 = z__h35304 ^ swd_controller_data[25] ; - assign z__h35318 = z__h35311 ^ swd_controller_data[26] ; - assign z__h35325 = z__h35318 ^ swd_controller_data[27] ; - assign z__h35332 = z__h35325 ^ swd_controller_data[28] ; - assign z__h35339 = z__h35332 ^ swd_controller_data[29] ; - assign z__h35346 = z__h35339 ^ swd_controller_data[30] ; - assign z__h35353 = z__h35346 ^ swd_controller_data[31] ; + assign swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d298 = + z__h35551 ^ swd_controller_data[32] ; + assign x__h1438 = _0xE79E__q2[i__h1457[3:0]] ; + assign x__h15006 = swd_controller_cnt - 7'd1 ; + assign x__h20247 = x__h20260 ^ cmd_BITS_1_TO_0__q1[1] ; + assign x__h20260 = x__h20262 ^ cmd_BITS_1_TO_0__q1[0] ; + assign x__h20262 = ~cmd[3] ; + assign x__h21446 = x__h21459 ^ cmd_BITS_1_TO_0__q1[1] ; + assign x__h21459 = cmd[3] ^ cmd_BITS_1_TO_0__q1[0] ; + assign z__h24693 = wdata[24] ^ wdata[25] ; + assign z__h24700 = z__h24693 ^ wdata[26] ; + assign z__h24707 = z__h24700 ^ wdata[27] ; + assign z__h24714 = z__h24707 ^ wdata[28] ; + assign z__h24721 = z__h24714 ^ wdata[29] ; + assign z__h24728 = z__h24721 ^ wdata[30] ; + assign z__h24735 = z__h24728 ^ wdata[31] ; + assign z__h24742 = z__h24735 ^ wdata[16] ; + assign z__h24749 = z__h24742 ^ wdata[17] ; + assign z__h24756 = z__h24749 ^ wdata[18] ; + assign z__h24763 = z__h24756 ^ wdata[19] ; + assign z__h24770 = z__h24763 ^ wdata[20] ; + assign z__h24777 = z__h24770 ^ wdata[21] ; + assign z__h24784 = z__h24777 ^ wdata[22] ; + assign z__h24791 = z__h24784 ^ wdata[23] ; + assign z__h24798 = z__h24791 ^ wdata[8] ; + assign z__h24805 = z__h24798 ^ wdata[9] ; + assign z__h24812 = z__h24805 ^ wdata[10] ; + assign z__h24819 = z__h24812 ^ wdata[11] ; + assign z__h24826 = z__h24819 ^ wdata[12] ; + assign z__h24833 = z__h24826 ^ wdata[13] ; + assign z__h24840 = z__h24833 ^ wdata[14] ; + assign z__h24847 = z__h24840 ^ wdata[15] ; + assign z__h24854 = z__h24847 ^ wdata[0] ; + assign z__h24861 = z__h24854 ^ wdata[1] ; + assign z__h24868 = z__h24861 ^ wdata[2] ; + assign z__h24875 = z__h24868 ^ wdata[3] ; + assign z__h24882 = z__h24875 ^ wdata[4] ; + assign z__h24889 = z__h24882 ^ wdata[5] ; + assign z__h24896 = z__h24889 ^ wdata[6] ; + assign z__h35341 = swd_controller_data[0] ^ swd_controller_data[1] ; + assign z__h35348 = z__h35341 ^ swd_controller_data[2] ; + assign z__h35355 = z__h35348 ^ swd_controller_data[3] ; + assign z__h35362 = z__h35355 ^ swd_controller_data[4] ; + assign z__h35369 = z__h35362 ^ swd_controller_data[5] ; + assign z__h35376 = z__h35369 ^ swd_controller_data[6] ; + assign z__h35383 = z__h35376 ^ swd_controller_data[7] ; + assign z__h35390 = z__h35383 ^ swd_controller_data[8] ; + assign z__h35397 = z__h35390 ^ swd_controller_data[9] ; + assign z__h35404 = z__h35397 ^ swd_controller_data[10] ; + assign z__h35411 = z__h35404 ^ swd_controller_data[11] ; + assign z__h35418 = z__h35411 ^ swd_controller_data[12] ; + assign z__h35425 = z__h35418 ^ swd_controller_data[13] ; + assign z__h35432 = z__h35425 ^ swd_controller_data[14] ; + assign z__h35439 = z__h35432 ^ swd_controller_data[15] ; + assign z__h35446 = z__h35439 ^ swd_controller_data[16] ; + assign z__h35453 = z__h35446 ^ swd_controller_data[17] ; + assign z__h35460 = z__h35453 ^ swd_controller_data[18] ; + assign z__h35467 = z__h35460 ^ swd_controller_data[19] ; + assign z__h35474 = z__h35467 ^ swd_controller_data[20] ; + assign z__h35481 = z__h35474 ^ swd_controller_data[21] ; + assign z__h35488 = z__h35481 ^ swd_controller_data[22] ; + assign z__h35495 = z__h35488 ^ swd_controller_data[23] ; + assign z__h35502 = z__h35495 ^ swd_controller_data[24] ; + assign z__h35509 = z__h35502 ^ swd_controller_data[25] ; + assign z__h35516 = z__h35509 ^ swd_controller_data[26] ; + assign z__h35523 = z__h35516 ^ swd_controller_data[27] ; + assign z__h35530 = z__h35523 ^ swd_controller_data[28] ; + assign z__h35537 = z__h35530 ^ swd_controller_data[29] ; + assign z__h35544 = z__h35537 ^ swd_controller_data[30] ; + assign z__h35551 = z__h35544 ^ swd_controller_data[31] ; // handling of inlined registers