From 0c999f29fbb49b0cab6ae40b64693ca69e325df8 Mon Sep 17 00:00:00 2001 From: cchr Date: Thu, 5 Sep 2024 16:36:40 +0200 Subject: [PATCH] Add trigger output --- api/scaffold/__init__.py | 12 +- fpga-arch/bsv/SWD.bsv | 12 +- fpga-arch/bsv/SWDInner.bsv | 2 +- fpga-arch/swd_module.v | 318 +++++++++++++++++++------------------ fpga-arch/system.vhd | 19 ++- 5 files changed, 199 insertions(+), 164 deletions(-) diff --git a/api/scaffold/__init__.py b/api/scaffold/__init__.py index 509f650..dffaa5e 100644 --- a/api/scaffold/__init__.py +++ b/api/scaffold/__init__.py @@ -1625,7 +1625,7 @@ def __init__(self, parent): """ super().__init__(parent, "/swd") # Declare the signals - self.add_signals("swclk", "swd_in", "swd_out") + self.add_signals("swclk", "swd_in", "swd_out", "trigger") # Declare the registers self.__addr_base = base = 0x0b00 self.add_register("rdata", "rv", base) @@ -1633,13 +1633,16 @@ def __init__(self, parent): self.add_register("status", "rv", base + 0x10) self.add_register("cmd", "w", base + 0x20) - def reset(self): + def reset(self, trigger=False): """ Reset the debug interface. This emits a reset sequence, followed by the JTAG-to-SWD select sequence and a second reset sequence. The deviceid register is then read. """ - self.reg_cmd.write(0x80) + val = 0x80 + if trigger: + val = val | (1 << 6) + self.reg_cmd.write(val) self.read(0, 0) return self.status() @@ -2340,6 +2343,8 @@ def connect( self.add_mtxl_in(f"/pgen{i}/out") for i in range(len(self.chains)): self.add_mtxl_in(f"/chain{i}/trigger") + if self.version >= parse_version("0.10"): + self.add_mtxl_in(f"/swd/trigger") # FPGA left matrix output signals # Update this section when adding new modules with inputs @@ -2397,6 +2402,7 @@ def connect( if self.version >= parse_version("0.10"): self.add_mtxr_in("/swd/swclk") self.add_mtxr_in("/swd/swd_out") + self.add_mtxr_in("/swd/trigger") # FPGA right matrix output signals self.add_mtxr_out("/io/a0") diff --git a/fpga-arch/bsv/SWD.bsv b/fpga-arch/bsv/SWD.bsv index 928b2b6..4f63e4b 100644 --- a/fpga-arch/bsv/SWD.bsv +++ b/fpga-arch/bsv/SWD.bsv @@ -45,11 +45,13 @@ endinterface interface ScaffoldSWDModule; (* prefix="" *) interface ScaffoldBus bus; (* prefix="" *) interface SWDControllerPins pins; + (* always_ready, prefix="" *) method Bit#(1) trigger; endinterface typedef struct { Bit#(1) reset; - Bit#(3) reserved; + Bit#(1) trigger; + Bit#(2) reserved; Bit#(1) apndp; Bit#(1) rnw; Bit#(2) addr; @@ -77,6 +79,8 @@ module swd_module (ScaffoldSWDModule); Reg#(Bit#(8)) bus_reg_rdata <- mkRegA(0); Reg#(Bit#(8)) bus_reg_status <- mkRegA(0); + PulseWire trig <- mkPulseWire(); + Reg#(Vector#(4, Bit#(8))) rdata <- mkRegA(unpack(0)); Reg#(Status) status <- mkRegA(unpack(0)); Reg#(Vector#(4, Bit#(8))) wdata <- mkRegA(unpack(0)); @@ -131,6 +135,10 @@ module swd_module (ScaffoldSWDModule); ); state <= RW; end + + if (new_cmd.trigger == 1) begin + trig.send(); + end endrule rule do_reset (state == RESET); @@ -184,4 +192,6 @@ module swd_module (ScaffoldSWDModule); endinterface interface SWDControllerPins pins = swd_controller.pins; + + method Bit#(1) trigger = pack(trig); endmodule \ No newline at end of file diff --git a/fpga-arch/bsv/SWDInner.bsv b/fpga-arch/bsv/SWDInner.bsv index dfa5bf3..7ac0d6d 100644 --- a/fpga-arch/bsv/SWDInner.bsv +++ b/fpga-arch/bsv/SWDInner.bsv @@ -157,7 +157,7 @@ module mkSWDController (SWDController#(clk_divider)) PulseWire reset_in <- mkPulseWire(); rule do_prescaler; - if (request_in) begin + if (request_in || reset_in) begin prescaler.reset(); end endrule diff --git a/fpga-arch/swd_module.v b/fpga-arch/swd_module.v index 07d8408..90ae02e 100644 --- a/fpga-arch/swd_module.v +++ b/fpga-arch/swd_module.v @@ -1,7 +1,7 @@ // // Generated by Bluespec Compiler, version 2024.01-9-gc481d7f5 (build c481d7f5) // -// On Wed Sep 4 10:01:30 CEST 2024 +// On Thu Sep 5 16:29:16 CEST 2024 // // // Ports: @@ -11,6 +11,7 @@ // swclk O 1 reg // swd_out O 1 reg // out_en O 1 reg +// trigger O 1 // CLK I 1 clock // RST_N I 1 reset // address I 16 unused @@ -23,7 +24,8 @@ // en_status I 1 // swd_in I 1 // -// No combinational paths from inputs to outputs +// Combinational paths from inputs to outputs: +// write -> trigger // // @@ -69,7 +71,9 @@ module swd_module(CLK, swd_out, - out_en); + out_en, + + trigger); input CLK; input RST_N; @@ -115,9 +119,12 @@ module swd_module(CLK, // value method pins_out_en output out_en; + // value method trigger + output trigger; + // signals for module outputs wire [7 : 0] reg_rdata, reg_status; - wire out_en, swclk, swd_out; + wire out_en, swclk, swd_out, trigger; // inlined wires wire swd_controller_request_in$whas, swd_controller_reset_in$whas; @@ -275,77 +282,77 @@ module swd_module(CLK, // remaining internal signals wire [15 : 0] _0xE79E__q2; - wire [6 : 0] i__h1364, x__h14824; + wire [6 : 0] i__h1365, x__h14825; wire [1 : 0] cmd_BITS_1_TO_0__q1; wire swd_controller_cnt_2_ULE_8___d35, - swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d300, - x__h1345, - x__h19907, - x__h19920, - x__h19922, - x__h21060, - x__h21073, - z__h24307, - z__h24314, - z__h24321, - z__h24328, - z__h24335, - z__h24342, - z__h24349, - z__h24356, - z__h24363, - z__h24370, - z__h24377, - z__h24384, - z__h24391, - z__h24398, - z__h24405, - z__h24412, - z__h24419, - z__h24426, - z__h24433, - z__h24440, - z__h24447, - z__h24454, - z__h24461, - z__h24468, - z__h24475, - z__h24482, - z__h24489, - z__h24496, - z__h24503, - z__h24510, - z__h34868, - z__h34875, - z__h34882, - z__h34889, - z__h34896, - z__h34903, - z__h34910, - z__h34917, - z__h34924, - z__h34931, - z__h34938, - z__h34945, - z__h34952, - z__h34959, - z__h34966, - z__h34973, - z__h34980, - z__h34987, - z__h34994, - z__h35001, - z__h35008, - z__h35015, - z__h35022, - z__h35029, - z__h35036, - z__h35043, - z__h35050, - z__h35057, - z__h35064, - z__h35071, - z__h35078; + swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301, + x__h1346, + x__h20049, + x__h20062, + x__h20064, + x__h21248, + x__h21261, + z__h24495, + z__h24502, + z__h24509, + z__h24516, + z__h24523, + z__h24530, + z__h24537, + z__h24544, + z__h24551, + z__h24558, + z__h24565, + z__h24572, + z__h24579, + z__h24586, + z__h24593, + z__h24600, + z__h24607, + z__h24614, + z__h24621, + z__h24628, + z__h24635, + z__h24642, + z__h24649, + z__h24656, + z__h24663, + z__h24670, + z__h24677, + z__h24684, + z__h24691, + z__h24698, + z__h35143, + z__h35150, + z__h35157, + z__h35164, + z__h35171, + z__h35178, + z__h35185, + z__h35192, + z__h35199, + z__h35206, + z__h35213, + z__h35220, + z__h35227, + z__h35234, + z__h35241, + z__h35248, + z__h35255, + z__h35262, + z__h35269, + z__h35276, + z__h35283, + z__h35290, + z__h35297, + z__h35304, + z__h35311, + z__h35318, + z__h35325, + z__h35332, + z__h35339, + z__h35346, + z__h35353; // value method bus_reg_rdata assign reg_rdata = bus_reg_rdata ; @@ -362,6 +369,9 @@ module swd_module(CLK, // value method pins_out_en assign out_en = swd_controller_out_en ; + // value method trigger + assign trigger = WILL_FIRE_RL_do_idle && cmd[6] ; + // submodule swd_controller_prescaler_ctr Counter #(.width(32'd8), .init(8'd99)) swd_controller_prescaler_ctr(.CLK(CLK), @@ -489,7 +499,7 @@ module swd_module(CLK, assign MUX_rdata$write_1__VAL_1 = { 8'd0, rdata[31:8] } ; assign MUX_rdata$write_1__VAL_2 = swd_controller_rnw ? - (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d300 ? + (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301 ? 32'd0 : swd_controller_data[31:0]) : 32'd0 ; @@ -500,22 +510,22 @@ module swd_module(CLK, swd_controller_request_in$whas ? 7'd10 : 7'd126 ; assign MUX_swd_controller_cnt$write_1__VAL_5 = (swd_controller_prescaler_ctr$Q_OUT == 8'd0) ? - x__h14824 : + x__h14825 : 7'd33 ; assign MUX_swd_controller_cnt$write_1__VAL_6 = - (swd_controller_prescaler_ctr$Q_OUT == 8'd0) ? x__h14824 : 7'd1 ; + (swd_controller_prescaler_ctr$Q_OUT == 8'd0) ? x__h14825 : 7'd1 ; assign MUX_swd_controller_data$write_1__VAL_1 = { swd_in, swd_controller_data[32:1] } ; assign MUX_swd_controller_data$write_1__VAL_2 = { 1'd0, swd_controller_data[32:1] } ; assign MUX_swd_controller_data$write_1__VAL_3 = - { z__h24510 ^ wdata[7], + { z__h24698 ^ wdata[7], wdata[7:0], wdata[15:8], wdata[23:16], wdata[31:24] } ; assign MUX_swd_controller_packet$write_1__VAL_2 = - { 1'd1, cmd[3:0], cmd[2] ? x__h19907 : x__h21060, 2'd1 } ; + { 1'd1, cmd[3:0], cmd[2] ? x__h20049 : x__h21248, 2'd1 } ; assign MUX_swd_controller_packet$write_1__VAL_3 = { swd_controller_packet[6:0], 1'd0 } ; assign MUX_swd_controller_state$write_1__VAL_1 = @@ -535,7 +545,7 @@ module swd_module(CLK, end assign MUX_swd_controller_swd_out$write_1__VAL_2 = swd_controller_cnt > 7'd71 || swd_controller_cnt <= 7'd55 || - x__h1345 ; + x__h1346 ; assign MUX_swd_controller_swd_out$write_1__VAL_3 = swd_controller_cnt_2_ULE_8___d35 && swd_controller_packet[7] ; @@ -587,7 +597,7 @@ module swd_module(CLK, // register status assign status$D_IN = swd_controller_rnw ? - (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d300 ? + (swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301 ? 2'd3 : swd_controller_status[1:0]) : swd_controller_status[1:0] ; @@ -601,7 +611,7 @@ module swd_module(CLK, // register swd_controller_cnt always@(MUX_swd_controller_cnt$write_1__SEL_1 or - x__h14824 or + x__h14825 or MUX_swd_controller_cnt$write_1__SEL_2 or MUX_swd_controller_cnt$write_1__VAL_2 or MUX_swd_controller_cnt$write_1__SEL_3 or @@ -614,7 +624,7 @@ module swd_module(CLK, begin case (1'b1) // synopsys parallel_case MUX_swd_controller_cnt$write_1__SEL_1: - swd_controller_cnt$D_IN = x__h14824; + swd_controller_cnt$D_IN = x__h14825; MUX_swd_controller_cnt$write_1__SEL_2: swd_controller_cnt$D_IN = MUX_swd_controller_cnt$write_1__VAL_2; MUX_swd_controller_cnt$write_1__SEL_3: swd_controller_cnt$D_IN = 7'd3; @@ -835,84 +845,84 @@ module swd_module(CLK, swd_controller_prescaler_ctr$Q_OUT != 8'd0 ; assign swd_controller_prescaler_ctr$SETC = 1'b0 ; assign swd_controller_prescaler_ctr$SETF = - swd_controller_request_in$whas || + swd_controller_request_in$whas || swd_controller_reset_in$whas || swd_controller_prescaler_ctr$Q_OUT == 8'd0 ; // remaining internal signals assign _0xE79E__q2 = 16'hE79E ; assign cmd_BITS_1_TO_0__q1 = cmd[1:0] ; - assign i__h1364 = 7'd71 - swd_controller_cnt ; + assign i__h1365 = 7'd71 - swd_controller_cnt ; assign swd_controller_cnt_2_ULE_8___d35 = swd_controller_cnt <= 7'd8 ; - assign swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d300 = - z__h35078 ^ swd_controller_data[32] ; - assign x__h1345 = _0xE79E__q2[i__h1364[3:0]] ; - assign x__h14824 = swd_controller_cnt - 7'd1 ; - assign x__h19907 = x__h19920 ^ cmd_BITS_1_TO_0__q1[1] ; - assign x__h19920 = x__h19922 ^ cmd_BITS_1_TO_0__q1[0] ; - assign x__h19922 = ~cmd[3] ; - assign x__h21060 = x__h21073 ^ cmd_BITS_1_TO_0__q1[1] ; - assign x__h21073 = cmd[3] ^ cmd_BITS_1_TO_0__q1[0] ; - assign z__h24307 = wdata[24] ^ wdata[25] ; - assign z__h24314 = z__h24307 ^ wdata[26] ; - assign z__h24321 = z__h24314 ^ wdata[27] ; - assign z__h24328 = z__h24321 ^ wdata[28] ; - assign z__h24335 = z__h24328 ^ wdata[29] ; - assign z__h24342 = z__h24335 ^ wdata[30] ; - assign z__h24349 = z__h24342 ^ wdata[31] ; - assign z__h24356 = z__h24349 ^ wdata[16] ; - assign z__h24363 = z__h24356 ^ wdata[17] ; - assign z__h24370 = z__h24363 ^ wdata[18] ; - assign z__h24377 = z__h24370 ^ wdata[19] ; - assign z__h24384 = z__h24377 ^ wdata[20] ; - assign z__h24391 = z__h24384 ^ wdata[21] ; - assign z__h24398 = z__h24391 ^ wdata[22] ; - assign z__h24405 = z__h24398 ^ wdata[23] ; - assign z__h24412 = z__h24405 ^ wdata[8] ; - assign z__h24419 = z__h24412 ^ wdata[9] ; - assign z__h24426 = z__h24419 ^ wdata[10] ; - assign z__h24433 = z__h24426 ^ wdata[11] ; - assign z__h24440 = z__h24433 ^ wdata[12] ; - assign z__h24447 = z__h24440 ^ wdata[13] ; - assign z__h24454 = z__h24447 ^ wdata[14] ; - assign z__h24461 = z__h24454 ^ wdata[15] ; - assign z__h24468 = z__h24461 ^ wdata[0] ; - assign z__h24475 = z__h24468 ^ wdata[1] ; - assign z__h24482 = z__h24475 ^ wdata[2] ; - assign z__h24489 = z__h24482 ^ wdata[3] ; - assign z__h24496 = z__h24489 ^ wdata[4] ; - assign z__h24503 = z__h24496 ^ wdata[5] ; - assign z__h24510 = z__h24503 ^ wdata[6] ; - assign z__h34868 = swd_controller_data[0] ^ swd_controller_data[1] ; - assign z__h34875 = z__h34868 ^ swd_controller_data[2] ; - assign z__h34882 = z__h34875 ^ swd_controller_data[3] ; - assign z__h34889 = z__h34882 ^ swd_controller_data[4] ; - assign z__h34896 = z__h34889 ^ swd_controller_data[5] ; - assign z__h34903 = z__h34896 ^ swd_controller_data[6] ; - assign z__h34910 = z__h34903 ^ swd_controller_data[7] ; - assign z__h34917 = z__h34910 ^ swd_controller_data[8] ; - assign z__h34924 = z__h34917 ^ swd_controller_data[9] ; - assign z__h34931 = z__h34924 ^ swd_controller_data[10] ; - assign z__h34938 = z__h34931 ^ swd_controller_data[11] ; - assign z__h34945 = z__h34938 ^ swd_controller_data[12] ; - assign z__h34952 = z__h34945 ^ swd_controller_data[13] ; - assign z__h34959 = z__h34952 ^ swd_controller_data[14] ; - assign z__h34966 = z__h34959 ^ swd_controller_data[15] ; - assign z__h34973 = z__h34966 ^ swd_controller_data[16] ; - assign z__h34980 = z__h34973 ^ swd_controller_data[17] ; - assign z__h34987 = z__h34980 ^ swd_controller_data[18] ; - assign z__h34994 = z__h34987 ^ swd_controller_data[19] ; - assign z__h35001 = z__h34994 ^ swd_controller_data[20] ; - assign z__h35008 = z__h35001 ^ swd_controller_data[21] ; - assign z__h35015 = z__h35008 ^ swd_controller_data[22] ; - assign z__h35022 = z__h35015 ^ swd_controller_data[23] ; - assign z__h35029 = z__h35022 ^ swd_controller_data[24] ; - assign z__h35036 = z__h35029 ^ swd_controller_data[25] ; - assign z__h35043 = z__h35036 ^ swd_controller_data[26] ; - assign z__h35050 = z__h35043 ^ swd_controller_data[27] ; - assign z__h35057 = z__h35050 ^ swd_controller_data[28] ; - assign z__h35064 = z__h35057 ^ swd_controller_data[29] ; - assign z__h35071 = z__h35064 ^ swd_controller_data[30] ; - assign z__h35078 = z__h35071 ^ swd_controller_data[31] ; + assign swd_controller_data_2_BIT_0_5_XOR_swd_controll_ETC___d301 = + z__h35353 ^ swd_controller_data[32] ; + assign x__h1346 = _0xE79E__q2[i__h1365[3:0]] ; + assign x__h14825 = swd_controller_cnt - 7'd1 ; + assign x__h20049 = x__h20062 ^ cmd_BITS_1_TO_0__q1[1] ; + assign x__h20062 = x__h20064 ^ cmd_BITS_1_TO_0__q1[0] ; + assign x__h20064 = ~cmd[3] ; + assign x__h21248 = x__h21261 ^ cmd_BITS_1_TO_0__q1[1] ; + assign x__h21261 = cmd[3] ^ cmd_BITS_1_TO_0__q1[0] ; + assign z__h24495 = wdata[24] ^ wdata[25] ; + assign z__h24502 = z__h24495 ^ wdata[26] ; + assign z__h24509 = z__h24502 ^ wdata[27] ; + assign z__h24516 = z__h24509 ^ wdata[28] ; + assign z__h24523 = z__h24516 ^ wdata[29] ; + assign z__h24530 = z__h24523 ^ wdata[30] ; + assign z__h24537 = z__h24530 ^ wdata[31] ; + assign z__h24544 = z__h24537 ^ wdata[16] ; + assign z__h24551 = z__h24544 ^ wdata[17] ; + assign z__h24558 = z__h24551 ^ wdata[18] ; + assign z__h24565 = z__h24558 ^ wdata[19] ; + assign z__h24572 = z__h24565 ^ wdata[20] ; + assign z__h24579 = z__h24572 ^ wdata[21] ; + assign z__h24586 = z__h24579 ^ wdata[22] ; + assign z__h24593 = z__h24586 ^ wdata[23] ; + assign z__h24600 = z__h24593 ^ wdata[8] ; + assign z__h24607 = z__h24600 ^ wdata[9] ; + assign z__h24614 = z__h24607 ^ wdata[10] ; + assign z__h24621 = z__h24614 ^ wdata[11] ; + assign z__h24628 = z__h24621 ^ wdata[12] ; + assign z__h24635 = z__h24628 ^ wdata[13] ; + assign z__h24642 = z__h24635 ^ wdata[14] ; + assign z__h24649 = z__h24642 ^ wdata[15] ; + assign z__h24656 = z__h24649 ^ wdata[0] ; + assign z__h24663 = z__h24656 ^ wdata[1] ; + assign z__h24670 = z__h24663 ^ wdata[2] ; + assign z__h24677 = z__h24670 ^ wdata[3] ; + assign z__h24684 = z__h24677 ^ wdata[4] ; + assign z__h24691 = z__h24684 ^ wdata[5] ; + assign z__h24698 = z__h24691 ^ wdata[6] ; + assign z__h35143 = swd_controller_data[0] ^ swd_controller_data[1] ; + assign z__h35150 = z__h35143 ^ swd_controller_data[2] ; + assign z__h35157 = z__h35150 ^ swd_controller_data[3] ; + assign z__h35164 = z__h35157 ^ swd_controller_data[4] ; + assign z__h35171 = z__h35164 ^ swd_controller_data[5] ; + assign z__h35178 = z__h35171 ^ swd_controller_data[6] ; + assign z__h35185 = z__h35178 ^ swd_controller_data[7] ; + assign z__h35192 = z__h35185 ^ swd_controller_data[8] ; + assign z__h35199 = z__h35192 ^ swd_controller_data[9] ; + assign z__h35206 = z__h35199 ^ swd_controller_data[10] ; + assign z__h35213 = z__h35206 ^ swd_controller_data[11] ; + assign z__h35220 = z__h35213 ^ swd_controller_data[12] ; + assign z__h35227 = z__h35220 ^ swd_controller_data[13] ; + assign z__h35234 = z__h35227 ^ swd_controller_data[14] ; + assign z__h35241 = z__h35234 ^ swd_controller_data[15] ; + assign z__h35248 = z__h35241 ^ swd_controller_data[16] ; + assign z__h35255 = z__h35248 ^ swd_controller_data[17] ; + assign z__h35262 = z__h35255 ^ swd_controller_data[18] ; + assign z__h35269 = z__h35262 ^ swd_controller_data[19] ; + assign z__h35276 = z__h35269 ^ swd_controller_data[20] ; + assign z__h35283 = z__h35276 ^ swd_controller_data[21] ; + assign z__h35290 = z__h35283 ^ swd_controller_data[22] ; + assign z__h35297 = z__h35290 ^ swd_controller_data[23] ; + assign z__h35304 = z__h35297 ^ swd_controller_data[24] ; + assign z__h35311 = z__h35304 ^ swd_controller_data[25] ; + assign z__h35318 = z__h35311 ^ swd_controller_data[26] ; + assign z__h35325 = z__h35318 ^ swd_controller_data[27] ; + assign z__h35332 = z__h35325 ^ swd_controller_data[28] ; + assign z__h35339 = z__h35332 ^ swd_controller_data[29] ; + assign z__h35346 = z__h35339 ^ swd_controller_data[30] ; + assign z__h35353 = z__h35346 ^ swd_controller_data[31] ; // handling of inlined registers diff --git a/fpga-arch/system.vhd b/fpga-arch/system.vhd index 4e8cb51..0d851fd 100644 --- a/fpga-arch/system.vhd +++ b/fpga-arch/system.vhd @@ -128,7 +128,8 @@ architecture behavior of system is swclk : OUT STD_LOGIC; swd_in : IN STD_LOGIC; swd_out : OUT STD_LOGIC; - out_en : OUT STD_LOGIC + out_en : OUT STD_LOGIC; + trigger : OUT STD_LOGIC ); END COMPONENT; @@ -174,6 +175,7 @@ architecture behavior of system is + 1 -- ISO7816 trigger + 1 -- I2C trigger + 1 -- SPI trigger + + 1 -- SWD trigger + pulse_gen_count -- Pulse generator outputs + chain_count; -- Chain trigger signal mtxl_in: std_logic_vector(mtxl_in_count-1 downto 0); @@ -211,7 +213,7 @@ architecture behavior of system is + 4 -- SPI module + 1 -- SPI slave module + 1 -- Clock - + 2; -- SWD + + 3; -- SWD signal mtxr_in: tristate_array_t(mtxr_in_count-1 downto 0); signal mtxr_in_uart_tx: std_logic_vector(uart_count-1 downto 0); signal mtxr_in_uart_trigger: std_logic_vector(uart_count-1 downto 0); @@ -233,6 +235,7 @@ architecture behavior of system is signal mtxr_in_swd_swdio: std_logic; signal mtxr_in_swd_swdio_en: std_logic; signal mtxr_in_swd_swclk: std_logic; + signal mtxr_in_swd_trigger: std_logic; signal mtxr_in_chain_out: std_logic_vector(chain_count-1 downto 0); -- Output signals of the output matrix @@ -742,6 +745,7 @@ begin output => mtxr_in_clock_out, glitch_start => mtxl_out_clock_glitch_start ); + -- SWD module c_swd: component swd_module port map ( CLK => clock, @@ -759,7 +763,8 @@ begin swclk => mtxr_in_swd_swclk, swd_in => mtxl_out_swd_swdio, swd_out => mtxr_in_swd_swdio, - out_en => mtxr_in_swd_swdio_en ); + out_en => mtxr_in_swd_swdio_en, + trigger => mtxr_in_swd_trigger ); -- Left matrix module e_left_matrix_module: entity work.left_matrix_module @@ -809,6 +814,7 @@ begin -- mtxr signals are feedback outputs of modules. -- Warning: signals order is inversed regarding Python API code. mtxl_in <= + mtxr_in_swd_trigger & mtxr_in_chain_out & mtxr_in_pulse_gen_out & mtxr_in_spi_trigger & @@ -855,7 +861,8 @@ begin mtxr_in_clock_out, mtxr_in_swd_swclk, mtxr_in_swd_swdio, - mtxr_in_swd_swdio_en + mtxr_in_swd_swdio_en, + mtxr_in_swd_trigger ) variable i: integer; begin @@ -904,9 +911,11 @@ begin -- Clock module mtxr_in(i) <= "1" & mtxr_in_clock_out; i := i + 1; + -- SWD module mtxr_in(i) <= "1" & mtxr_in_swd_swclk; mtxr_in(i+1) <= mtxr_in_swd_swdio_en & mtxr_in_swd_swdio; - i := i + 2; + mtxr_in(i+2) <= "1" & mtxr_in_swd_trigger; + i := i + 3; -- If you add other signals, please dont forget to update the sensivity -- list for simulation support. assert i = mtxr_in_count;