diff --git a/.github/workflows/installer.yml b/.github/workflows/installer.yml index 5929d94f2..0dff54fe7 100644 --- a/.github/workflows/installer.yml +++ b/.github/workflows/installer.yml @@ -28,6 +28,13 @@ jobs: - cepheus - vayu-huaxing - vayu-tianma + # sm8250 + - lmi + # sm8550 + - fuxi + # sm7325 + - lisa + # Steps represent a sequence of tasks that will be executed as part of the job steps: diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml index 8bb74d810..b505bb194 100644 --- a/.github/workflows/main.yml +++ b/.github/workflows/main.yml @@ -31,7 +31,9 @@ jobs: - cepheus - hotdog - guacamole + - guacamoleb # sdm845 + - fajita - beryllium-ebbg - beryllium-tianma - polaris @@ -50,12 +52,12 @@ jobs: - name: Install required packages run: | - sudo dpkg --add-architecture i386 + sudo dpkg --add-architecture i386 wget -qO - https://dl.winehq.org/wine-builds/winehq.key | sudo apt-key add - sudo add-apt-repository ppa:cybermax-dexter/sdl2-backport sudo apt-add-repository "deb https://dl.winehq.org/wine-builds/ubuntu $(lsb_release -cs) main" sudo apt-get update - sudo apt-get -y install build-essential uuid-dev clang llvm iasl nasm gcc-aarch64-linux-gnu abootimg python3-distutils python3-pil python3-git gettext + sudo apt-get -y install build-essential uuid-dev clang llvm iasl nasm gcc-aarch64-linux-gnu abootimg python3-distutils python3-pil python3-git gettext libgcc-s1:i386 libstdc++6:i386 sudo apt-get install --install-recommends winehq-stable - name: Build an image for ${{ matrix.device }} diff --git a/Platform/Asus/sdm660/FdtBlob_compat/x00td.dtb b/Platform/Asus/sdm660/FdtBlob_compat/x00td.dtb new file mode 100644 index 000000000..cea2d6db0 Binary files /dev/null and b/Platform/Asus/sdm660/FdtBlob_compat/x00td.dtb differ diff --git a/Platform/Asus/sdm660/x00td.dsc b/Platform/Asus/sdm660/x00td.dsc new file mode 100644 index 000000000..a49314ab8 --- /dev/null +++ b/Platform/Asus/sdm660/x00td.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = ASUS + PLATFORM_NAME = x00td + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sdm660/sdm660.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Asus/sdm660/x00td.fdf.inc + +!include Platform/Qualcomm/sdm660/sdm660.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2160 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|420 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Asus" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"MaxProM1" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"X00TD" diff --git a/Platform/Asus/sdm660/x00td.fdf.inc b/Platform/Asus/sdm660/x00td.fdf.inc new file mode 100644 index 000000000..1717f68ba --- /dev/null +++ b/Platform/Asus/sdm660/x00td.fdf.inc @@ -0,0 +1,16 @@ +// per-device BSP DXEs + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/DSDT/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/FACS.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/FADT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/MADT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/MCFG.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob diff --git a/Platform/EFI_Binaries b/Platform/EFI_Binaries index 87ac13a39..d097b8a8b 160000 --- a/Platform/EFI_Binaries +++ b/Platform/EFI_Binaries @@ -1 +1 @@ -Subproject commit 87ac13a39d88790fd1a7f4bf5550f14aa3d8ed15 +Subproject commit d097b8a8bf3641e5e0c8b36ef1ac9d7cc1a0bd94 diff --git a/Platform/LG/sm8150/AcpiTables/flashlmdd/DSDT.aml b/Platform/LG/sm8150/AcpiTables/flashlmdd/DSDT.aml new file mode 100755 index 000000000..c88bdec90 Binary files /dev/null and b/Platform/LG/sm8150/AcpiTables/flashlmdd/DSDT.aml differ diff --git a/Platform/LG/sm8150/AcpiTables/mh2lm/DSDT.aml b/Platform/LG/sm8150/AcpiTables/mh2lm/DSDT.aml index 728cdef39..1732d03b8 100755 Binary files a/Platform/LG/sm8150/AcpiTables/mh2lm/DSDT.aml and b/Platform/LG/sm8150/AcpiTables/mh2lm/DSDT.aml differ diff --git a/Platform/LG/sm8150/AcpiTables/mh2lm5g/DSDT.aml b/Platform/LG/sm8150/AcpiTables/mh2lm5g/DSDT.aml new file mode 100644 index 000000000..a531f189e Binary files /dev/null and b/Platform/LG/sm8150/AcpiTables/mh2lm5g/DSDT.aml differ diff --git a/Platform/LG/sm8150/FdtBlob_compat/flashlmdd.dtb b/Platform/LG/sm8150/FdtBlob_compat/flashlmdd.dtb new file mode 100755 index 000000000..3a95eb6de Binary files /dev/null and b/Platform/LG/sm8150/FdtBlob_compat/flashlmdd.dtb differ diff --git a/Platform/LG/sm8150/FdtBlob_compat/mh2lm5g.dtb b/Platform/LG/sm8150/FdtBlob_compat/mh2lm5g.dtb new file mode 100644 index 000000000..83946926e Binary files /dev/null and b/Platform/LG/sm8150/FdtBlob_compat/mh2lm5g.dtb differ diff --git a/Platform/LG/sm8150/betalm.fdf.inc b/Platform/LG/sm8150/betalm.fdf.inc index 9eb4e3cc8..06736f7aa 100644 --- a/Platform/LG/sm8150/betalm.fdf.inc +++ b/Platform/LG/sm8150/betalm.fdf.inc @@ -24,12 +24,6 @@ FILE DRIVER = f10f76db-42c1-533f-34a8-69be24653110 { SECTION UI = "SdccDxe" } -FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { - SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex - SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi - SECTION UI = "UsbPwrCtrlDxe" -} - // ACPI Tables FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { diff --git a/Platform/LG/sm8150/flashlmdd.dsc b/Platform/LG/sm8150/flashlmdd.dsc new file mode 100755 index 000000000..c80f317ac --- /dev/null +++ b/Platform/LG/sm8150/flashlmdd.dsc @@ -0,0 +1,39 @@ +[Defines] + VENDOR_NAME = LG + PLATFORM_NAME = flashlmdd + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8150/sm8150.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/LG/sm8150/flashlmdd.fdf.inc + +!include Platform/Qualcomm/sm8150/sm8150.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DMEMMAP_LG_HACKS + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1440 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|3120 + # gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9D200000 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|355 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"LG" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"V50 ThinQ" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"flashlmdd" + + # Synaptics Touchscren + # gQcomTokenSpaceGuid.PcdTouchCtlrAddress|0x20 + # gQcomTokenSpaceGuid.PcdTouchCtlrResetPin|54 + # gQcomTokenSpaceGuid.PcdTouchCtlrIntPin|122 + # gQcomTokenSpaceGuid.PcdTouchCtlrI2cDevice|18 + # gQcomTokenSpaceGuid.PcdTouchMaxX|1080 + # gQcomTokenSpaceGuid.PcdTouchMaxY|2340 + # gQcomTokenSpaceGuid.PcdTouchCtlrVddPin|59 + # gQcomTokenSpaceGuid.PcdTouchCtlrVddIoPin|152 diff --git a/Platform/LG/sm8150/flashlmdd.fdf.inc b/Platform/LG/sm8150/flashlmdd.fdf.inc new file mode 100755 index 000000000..fc784e100 --- /dev/null +++ b/Platform/LG/sm8150/flashlmdd.fdf.inc @@ -0,0 +1,57 @@ +// per-device BSP DXEs + +FILE DRIVER = 8e9bd160-b184-11df-94e2-0800200c9a66 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/DALSys/DALSys.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/mh2lm/DALSys/DALSys.efi + SECTION UI = "DALSys" +} + +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/mh2lm/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +FILE DRIVER = f10f76db-42c1-533f-34a8-69be24653110 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/SdccDxe/SdccDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/SdccDxe/SdccDxe.efi + SECTION UI = "SdccDxe" + } + +FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" +} + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + +# Customized DSDT + SECTION RAW = Platform/LG/sm8150/AcpiTables/flashlmdd/DSDT.aml +# Common Tables + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/APIC.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BERT.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BGRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FACP.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FPDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/IORT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MCFG.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MSDM.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/PPTT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/TPM2.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/XSDT.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob + + + # + # Touchscreen + # + # INF Silicon/Qualcomm/QcomPkg/Drivers/SynapticsTCMDxe/SynapticsTCMDevice.inf + # INF Silicon/Qualcomm/QcomPkg/Drivers/SynapticsTCMDxe/SynapticsTCMDxe.inf \ No newline at end of file diff --git a/Platform/LG/sm8150/mh2lm5g.dsc b/Platform/LG/sm8150/mh2lm5g.dsc new file mode 100644 index 000000000..b56f0454a --- /dev/null +++ b/Platform/LG/sm8150/mh2lm5g.dsc @@ -0,0 +1,39 @@ +[Defines] + VENDOR_NAME = LG + PLATFORM_NAME = mh2lm5g + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8150/sm8150.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/LG/sm8150/mh2lm5g.fdf.inc + +!include Platform/Qualcomm/sm8150/sm8150.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DPLST_FIX -DMEMMAP_LG_HACKS -DHAS_MLVM + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2340 + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9C000000 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|355 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"LG" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"V50s ThinQ" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"mh2lm5G" + + # Synaptics Touchscren + gQcomTokenSpaceGuid.PcdTouchCtlrAddress|0x20 + gQcomTokenSpaceGuid.PcdTouchCtlrResetPin|54 + gQcomTokenSpaceGuid.PcdTouchCtlrIntPin|122 + gQcomTokenSpaceGuid.PcdTouchCtlrI2cDevice|18 + gQcomTokenSpaceGuid.PcdTouchMaxX|1080 + gQcomTokenSpaceGuid.PcdTouchMaxY|2340 + gQcomTokenSpaceGuid.PcdTouchCtlrVddPin|59 + gQcomTokenSpaceGuid.PcdTouchCtlrVddIoPin|152 diff --git a/Platform/LG/sm8150/mh2lm5g.fdf.inc b/Platform/LG/sm8150/mh2lm5g.fdf.inc new file mode 100644 index 000000000..79b0019ca --- /dev/null +++ b/Platform/LG/sm8150/mh2lm5g.fdf.inc @@ -0,0 +1,57 @@ +// per-device BSP DXEs + +FILE DRIVER = 8e9bd160-b184-11df-94e2-0800200c9a66 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/DALSys/DALSys.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/mh2lm5g/DALSys/DALSys.efi + SECTION UI = "DALSys" +} + +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/mh2lm5g/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +FILE DRIVER = f10f76db-42c1-533f-34a8-69be24653110 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/SdccDxe/SdccDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/SdccDxe/SdccDxe.efi + SECTION UI = "SdccDxe" + } + +FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" +} + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + +# Customized DSDT + SECTION RAW = Platform/LG/sm8150/AcpiTables/mh2lm5g/DSDT.aml +# Common Tables + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/APIC.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BERT.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BGRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FACP.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FPDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/IORT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MCFG.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MSDM.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/PPTT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/TPM2.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/XSDT.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob + + + # + # Touchscreen + # + # INF Silicon/Qualcomm/QcomPkg/Drivers/SynapticsTCMDxe/SynapticsTCMDevice.inf + # INF Silicon/Qualcomm/QcomPkg/Drivers/SynapticsTCMDxe/SynapticsTCMDxe.inf \ No newline at end of file diff --git a/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/DSDT.aml b/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/DSDT.aml new file mode 100644 index 000000000..6890558b3 Binary files /dev/null and b/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/DSDT.aml differ diff --git a/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/Dsdt.asl b/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/Dsdt.asl new file mode 100644 index 000000000..dbe7b2285 --- /dev/null +++ b/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/Dsdt.asl @@ -0,0 +1,24 @@ +// +// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support. +// +DefinitionBlock("DSDT.AML", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3) +{ + Scope(\_SB_) { + + // Include("addSub.asl") + Include("dsdt_common.asl") + // Include("cust_dsdt.asl") + + // Include("usb.asl") + + // + // Buttons + // + // Include("cust_arraybutton.asl") + + // + // Bluetooth + // + // Include("wcnss_bt.asl") + } +} diff --git a/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/dsdt_common.asl b/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/dsdt_common.asl new file mode 100644 index 000000000..b60b66782 --- /dev/null +++ b/Platform/Lenovo/sm8250/AcpiTables/tb-9707f/dsdt_common.asl @@ -0,0 +1,103 @@ +Name(SOID, 0xffffffff) // Holds the Chip Id +Name(STOR, 0x1) // Holds boot options 0 = nvme, 1 = ufs +Name(SIDS, "899800000000000") // Holds the Chip ID translated to a string +Name(SIDV, 0xffffffff) // Holds the Chip Version as (major<<16)|(minor&0xffff) +Name(SVMJ, 0xffff) // Holds the major Chip Version +Name(SVMI, 0xffff) // Holds the minor Chip Version +Name(SDFE, 0xffff) // Holds the Chip Family enum +Name(SFES, "899800000000000") // Holds the Chip Family translated to a string +Name(SIDM, 0xfffffffff) // Holds the Modem Support bit field +Name(SUFS, 0x0) // Holds secondary UFS enablement (1 = enabled) +Name(PUS3, 0x0) // Holds whether primary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SUS3, 0x0) // Holds whether secondary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SIDT, 0xffffffff) // Holds the Chip Tier value +Name(SJTG, 0xffffffff) // Holds the JTAG ID +Name(SOSN, 0xaaaaaaaabbbbbbbb) // Holds the Chip Serial Number +Name(PLST, 0xffffffff) // Holds the Device platform subtype +Name(EMUL, 0xffffffff) // Holds the Device emulation type +Name (RMTB, 0xaaaaaaaa) // Holds the RemoteFS shared memory base address +Name (RMTX, 0xbbbbbbbb) // Holds the RemoteFS shared memory length +Name (RFMB, 0xcccccccc) // Holds the RFSA MPSS shared memory base address +Name (RFMS, 0xdddddddd) // Holds the RFSA MPSS shared memory length +Name (RFAB, 0xeeeeeeee) // Holds the RFSA ADSP shared memory base address +Name (RFAS, 0x77777777) // Holds the RFSA ADSP shared memory length +Name (TCMA, 0xDEADBEEF) // Holds TrEE Carveout Memory Address +Name (TCML, 0xBEEFDEAD) // Holds TrEE Carveout Memory Length +Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib +Name (PRP1, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 1 present : 0x00000000 - PCIe root port 1 not present +Name (SKUV, 0x1) // Set SKU Version to 1 + +//Audio Drivers +// Include("audio.asl") + + // + // Storage - UFS/SD + // + Include("ufs.asl") + // Include("sdc.asl") // No SD support on polaris + + // + // ASL Bridge Device + // + // Include("abd.asl") + + Name (ESNL, 20) // Exsoc name limit 20 characters + Name (DBFL, 23) // buffer Length, should be ESNL+3 + +// +// PMIC driver +// +// Include("pmic_core.asl") + +// +// PMICTCC driver +// +// Include("pmic_batt.asl") + + // Include("pep.asl") + // Include("bam.asl") + // Include("buses.asl") + + // MPROC Drivers (PIL Driver and Subsystem Drivers) + // Include("win_mproc.asl") + // Include("syscache.asl") + // Include("HoyaSmmu.asl") + // Include("graphics.asl") + + // Include("SCM.asl"); + + // + // SPMI driver + // + // Include("spmi.asl") + + // + // TLMM controller. + // + // Include("qcgpio.asl") + + // Include("pcie.asl") + + // Include("cbsp_mproc.asl") + + // Include("adsprpc.asl") + + // + // RemoteFS + // + // Include("rfs.asl") + + // + // Qualcomm IPA + // Include("ipa.asl") + + // Include("gsi.asl") + + // Include("qcdb.asl") + + // copied from sm7325, need to check + Include("Pep_lpi.asl") + +// QUPV3 GPI device node and resources +// +// Include("qgpi.asl") diff --git a/Platform/Lenovo/sm8250/FdtBlob_compat/tb-9707f.dtb b/Platform/Lenovo/sm8250/FdtBlob_compat/tb-9707f.dtb new file mode 100644 index 000000000..2c4595a2f Binary files /dev/null and b/Platform/Lenovo/sm8250/FdtBlob_compat/tb-9707f.dtb differ diff --git a/Platform/Lenovo/sm8250/Library/tb-9707f/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Platform/Lenovo/sm8250/Library/tb-9707f/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..11a8f9da4 --- /dev/null +++ b/Platform/Lenovo/sm8250/Library/tb-9707f/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,69 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { + /* Hypervisor seems needed for windows boot? */ + {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"HLOS 1", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"AOP", 0x80700000, 0x00160000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"XBL Log Buffer", 0x80880000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"HLOS 2", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"Removed Mem", 0x80b00000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"PIL Reserved", 0x86200000, 0x05D00000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 3", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x9C000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"DBI Dump", 0x9E400000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 4", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"HLOS 5", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + + {"HLOS 6", 0xA0000000, 0x10000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + /* Set pstore size to 0x00500000, otherwise OnePlus 8 Pro will crashdump. */ + {"PSTORE", 0xB0000000, 0x00500000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"HLOS 7", 0xB0400000, 0x0C800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + {"DXE Heap", 0xC0000000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + + {"RAM Partition", 0xD0000000,0x130000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + /* Other memory regions */ + {"IMEM Base", 0x14680000, 0x00040000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x146BF000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + /* Register regions */ + {"IPC_ROUTER_TOP", 0x00400000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_2_GSI", 0x00800000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x00900000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x00A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x00790000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TCSR_TCSR_REGS", 0x01FC0000, 0x00030000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x02C7D000, 0x00002000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x02C90000, 0x0000A000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_SSC_GSI", 0x05A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x08800000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x0A600000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB_RUMI", 0x0A720000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_SEC", 0x0A800000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"AOSS", 0x0B000000, 0x04000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x0F100000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x0F500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_NORTH", 0x0F900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_HM", 0x17800000, 0x0d981000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"Terminator", 0, 0, 0, 0, 0, 0, 0} +}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} diff --git a/Platform/Lenovo/sm8250/Library/tb-9707f/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Platform/Lenovo/sm8250/Library/tb-9707f/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Platform/Lenovo/sm8250/Library/tb-9707f/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Platform/Lenovo/sm8250/tb-9707f.dsc b/Platform/Lenovo/sm8250/tb-9707f.dsc new file mode 100644 index 000000000..23c9c2ce6 --- /dev/null +++ b/Platform/Lenovo/sm8250/tb-9707f.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Lenovo + PLATFORM_NAME = tb-9707f + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8250/sm8250.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Lenovo/sm8250/tb-9707f.fdf.inc + +!include Platform/Qualcomm/sm8250/sm8250.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1600 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2560 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|400 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Lenovo" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Legion Tab Y700" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"TB-9707F" diff --git a/Platform/Lenovo/sm8250/tb-9707f.fdf.inc b/Platform/Lenovo/sm8250/tb-9707f.fdf.inc new file mode 100644 index 000000000..ca4fead7f --- /dev/null +++ b/Platform/Lenovo/sm8250/tb-9707f.fdf.inc @@ -0,0 +1,16 @@ +//ButtonsDxe +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8250/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8250/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Platform/Lenovo/sm8250/AcpiTables/tb-9707f/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Madt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Facp.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Gtdt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/bgrt.aml + SECTION UI = "AcpiTables" +} diff --git a/Platform/Oneplus/sm8150/AcpiTables/guacamoleb/DSDT.aml b/Platform/Oneplus/sm8150/AcpiTables/guacamoleb/DSDT.aml index 7e15aa363..6ab98c29c 100644 Binary files a/Platform/Oneplus/sm8150/AcpiTables/guacamoleb/DSDT.aml and b/Platform/Oneplus/sm8150/AcpiTables/guacamoleb/DSDT.aml differ diff --git a/Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-guacamoleb.dtb b/Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-hotdogb.dtb similarity index 100% rename from Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-guacamoleb.dtb rename to Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-hotdogb.dtb diff --git a/Platform/Oneplus/sm8150/FdtBlob_compat/guacamoleb.dtb b/Platform/Oneplus/sm8150/FdtBlob_compat/guacamoleb.dtb index 6c9dd6bdd..110e16a9a 100644 Binary files a/Platform/Oneplus/sm8150/FdtBlob_compat/guacamoleb.dtb and b/Platform/Oneplus/sm8150/FdtBlob_compat/guacamoleb.dtb differ diff --git a/Platform/Oneplus/sm8150/FdtBlob_compat/hotdogb.dtb b/Platform/Oneplus/sm8150/FdtBlob_compat/hotdogb.dtb new file mode 100644 index 000000000..690af529c Binary files /dev/null and b/Platform/Oneplus/sm8150/FdtBlob_compat/hotdogb.dtb differ diff --git a/Platform/Oneplus/sm8150/guacamoleb.dsc b/Platform/Oneplus/sm8150/guacamoleb.dsc index 7b6f6008c..ad9bee1e7 100644 --- a/Platform/Oneplus/sm8150/guacamoleb.dsc +++ b/Platform/Oneplus/sm8150/guacamoleb.dsc @@ -10,11 +10,13 @@ SKUID_IDENTIFIER = DEFAULT FLASH_DEFINITION = Platform/Qualcomm/sm8150/sm8150.fdf DEVICE_DXE_FV_COMPONENTS = Platform/Oneplus/sm8150/guacamoleb.fdf.inc + # Enable A/B Slot Environment + AB_SLOTS_SUPPORT = TRUE !include Platform/Qualcomm/sm8150/sm8150.dsc [BuildOptions.common] - GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + GCC:*_*_AARCH64_CC_FLAGS = -DAB_SLOTS_SUPPORT=1 -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE [PcdsFixedAtBuild.common] gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 diff --git a/Platform/Oneplus/sm8150/guacamoleb.fdf.inc b/Platform/Oneplus/sm8150/guacamoleb.fdf.inc index e9d2da74d..a3df9c8af 100644 --- a/Platform/Oneplus/sm8150/guacamoleb.fdf.inc +++ b/Platform/Oneplus/sm8150/guacamoleb.fdf.inc @@ -1,26 +1,26 @@ -// per-device BSP DXEs (use from op7 pro) +// per-device BSP DXEs FILE DRIVER = 8e9bd160-b184-11df-94e2-0800200c9a66 { SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/DALSys/DALSys.depex - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamole/DALSys/DALSys.efi + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamoleb/DALSys/DALSys.efi SECTION UI = "DALSys" } FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/ButtonsDxe/ButtonsDxe.depex - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamole/ButtonsDxe/ButtonsDxe.efi + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamoleb/ButtonsDxe/ButtonsDxe.efi SECTION UI = "ButtonsDxe" } FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { - SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex - SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamole/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi - SECTION UI = "UsbPwrCtrlDxe" + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamoleb/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" } -// ACPI Tables (use from op7 pro) +// ACPI Tables FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { # Customized DSDT - SECTION RAW = Platform/Oneplus/sm8150/AcpiTables/guacamole/DSDT.aml + SECTION RAW = Platform/Oneplus/sm8150/AcpiTables/guacamoleb/DSDT.aml # Common Tables SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/APIC.aml # SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BERT.aml @@ -39,7 +39,7 @@ FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { SECTION UI = "AcpiTables" } -// Mainline device tree blob (use from sm-8150 mainlane - https://gitlab.com/sm8150-mainline/linux/-/blob/sm8150/5.17/arch/arm64/boot/dts/qcom/sm8150-oneplus-hotdogb.dts) +// Mainline device tree blob (use from sm-8150 mainline - https://gitlab.com/sm8150-mainline/linux/-/blob/sm8150/5.17/arch/arm64/boot/dts/qcom/sm8150-oneplus-hotdogb.dts) FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { - SECTION RAW = Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-guacamoleb.dtb + SECTION RAW = Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-hotdogb.dtb } diff --git a/Platform/Oneplus/sm8150/hotdogb.dsc b/Platform/Oneplus/sm8150/hotdogb.dsc new file mode 100755 index 000000000..db490b1e3 --- /dev/null +++ b/Platform/Oneplus/sm8150/hotdogb.dsc @@ -0,0 +1,32 @@ +[Defines] + VENDOR_NAME = Oneplus + PLATFORM_NAME = hotdogb + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8150/sm8150.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Oneplus/sm8150/hotdogb.fdf.inc + # Enable A/B Slot Environment + AB_SLOTS_SUPPORT = TRUE + +!include Platform/Qualcomm/sm8150/sm8150.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DAB_SLOTS_SUPPORT=1 -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2400 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|401 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"OnePlus" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"7T" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"hotdogb" + + gsm8150PkgTokenSpaceGuid.PcdSmbiosProcessorModel|"Snapdragon (TM) 855 Plus @ 2.96 GHz" diff --git a/Platform/Oneplus/sm8150/hotdogb.fdf.inc b/Platform/Oneplus/sm8150/hotdogb.fdf.inc new file mode 100644 index 000000000..d0a8fa15b --- /dev/null +++ b/Platform/Oneplus/sm8150/hotdogb.fdf.inc @@ -0,0 +1,45 @@ +// per-device BSP DXEs (use from op7 pro) +FILE DRIVER = 8e9bd160-b184-11df-94e2-0800200c9a66 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/DALSys/DALSys.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamole/DALSys/DALSys.efi + SECTION UI = "DALSys" +} + +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamole/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/guacamole/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" +} + +// ACPI Tables (use from op7 pro) +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { +# Customized DSDT + SECTION RAW = Platform/Oneplus/sm8150/AcpiTables/guacamole/DSDT.aml +# Common Tables + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/APIC.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BERT.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BGRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FACP.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FPDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/IORT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MCFG.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MSDM.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/PPTT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/TPM2.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/XSDT.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob (use from sm-8150 mainlane - https://gitlab.com/sm8150-mainline/linux/-/blob/sm8150/5.17/arch/arm64/boot/dts/qcom/sm8150-oneplus-hotdogb.dts) +FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/Oneplus/sm8150/FdtBlob/sm8150-oneplus-hotdogb.dtb +} diff --git a/Platform/Qualcomm/sdm845/sdm845.fdf b/Platform/Qualcomm/sdm845/sdm845.fdf index 60a05b55b..8bb9b5f57 100644 --- a/Platform/Qualcomm/sdm845/sdm845.fdf +++ b/Platform/Qualcomm/sdm845/sdm845.fdf @@ -31,7 +31,7 @@ ErasePolarity = 1 # This one is tricky, it must be: BlockSize * NumBlocks = Size BlockSize = 0x00001000 -NumBlocks = 0x2000 +NumBlocks = 0x700 ################################################################################ # @@ -49,7 +49,7 @@ NumBlocks = 0x2000 # ################################################################################ -0x00000000|0x02000000 +0x00000000|0x00700000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT @@ -214,6 +214,15 @@ READ_LOCK_STATUS = TRUE INF GPLDrivers/Application/SwitchSlotsApp/SwitchSlotsApp.inf !endif +!if $(ENABLE_LINUX_UTILS) == 1 + FILE FREEFORM = 4b0364cf-1c5b-47aa-9073-d7b5039ce49b { + SECTION RAW = tools/simpleinit.static.uefi.cfg + SECTION UI = "simpleinit.static.uefi.cfg" + } + + INF Platform/RenegadePkg/Application/Reboot2PayloadApp/Reboot2PayloadApp.inf +!endif + # Device specific fdf !include $(DEVICE_DXE_FV_COMPONENTS) diff --git a/Platform/Qualcomm/sm6225/Apriori.fdf.inc b/Platform/Qualcomm/sm6225/Apriori.fdf.inc new file mode 100644 index 000000000..d0f3f163f --- /dev/null +++ b/Platform/Qualcomm/sm6225/Apriori.fdf.inc @@ -0,0 +1,84 @@ +APRIORI DXE { + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/HWIODxe/HWIODxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ChipInfoDxe/ChipInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PlatformInfoDxe/PlatformInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/HALIOMMUDxe/HALIOMMUDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/GLinkDxe/GLinkDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ULogDxe/ULogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/NpaDxe/NpaDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/VcsDxe/VcsDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ClockDxe/ClockDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UFSDxe/UFSDxe.inf + + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SPMIDxe/SPMIDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf + + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/I2CDxe/I2CDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ChargerExDxe/ChargerExDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbConfigDxe/UsbConfigDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf + + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf + + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf +} \ No newline at end of file diff --git a/Platform/Qualcomm/sm6225/dxe.fdf.inc b/Platform/Qualcomm/sm6225/dxe.fdf.inc new file mode 100644 index 000000000..9219c25cb --- /dev/null +++ b/Platform/Qualcomm/sm6225/dxe.fdf.inc @@ -0,0 +1,42 @@ + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/ScmDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TzDxe/TzDxeLA.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/FontDxe/FontDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/QcomWDogDxe/QcomWDogDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/ChipInfoDxe/ChipInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/GLinkDxe/GLinkDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SmemDxe/SmemDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ULogDxe/ULogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/NpaDxe/NpaDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/DALSYSDxe/DALSYSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/VcsDxe/VcsDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ClockDxe/ClockDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/HALIOMMUDxe/HALIOMMUDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/HWIODxe/HWIODxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/GpiDxe/GpiDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/I2CDxe/I2CDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SPMIDxe/SPMIDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/SdccDxe/SdccDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UFSDxe/UFSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TLMMDxe/TLMMDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/PlatformInfoDxe/PlatformInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/PmicDxe/PmicDxeLa.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ChargerExDxe/ChargerExDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/QcomChargerDxe/QcomChargerDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/AdcDxe/AdcDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/TsensDxe/TsensDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/DDRInfoDxe/DDRInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/UsbMsdDxe/UsbMsdDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbDeviceDxe/UsbDeviceDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/UsbConfigDxe/UsbConfigDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6225/PILDxe/PILDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ShmBridgeDxe/ShmBridgeDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6225/ResetRuntimeDxe/ResetRuntimeDxe.inf \ No newline at end of file diff --git a/Platform/Qualcomm/sm6225/sm6225.dsc b/Platform/Qualcomm/sm6225/sm6225.dsc new file mode 100644 index 000000000..e62fe128a --- /dev/null +++ b/Platform/Qualcomm/sm6225/sm6225.dsc @@ -0,0 +1,67 @@ +## @file +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. +# Copyright (c) 2018 - 2019, Bingxing Wang. All rights reserved. +# Copyright (c) 2022, Xilin Wu. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ + +[Defines] + SOC_PLATFORM = sm6225 + USE_PHYSICAL_TIMER = TRUE + +!include Silicon/Qualcomm/QcomPkg/QcomCommonDsc.inc + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000 # Starting address + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x5FF8C000 # CPU Vectors + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|19200000 + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|18 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|20 + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|30 + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26 + gArmTokenSpaceGuid.PcdGicDistributorBase|0xf200000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xf300000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xf200000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00006225 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x5FF90000 # UEFI Stack + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x00040000 # 256K stack + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 + + gQcomTokenSpaceGuid.PcdUefiMemPoolBase|0x63900000 # DXE Heap base address + gQcomTokenSpaceGuid.PcdUefiMemPoolSize|0x0E000000 # UefiMemorySize, DXE heap size + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x5C000000 + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # + # SimpleInit + # + gSimpleInitTokenSpaceGuid.PcdDeviceTreeStore|0x53F00000 + gSimpleInitTokenSpaceGuid.PcdLoggerdUseConsole|FALSE + +[LibraryClasses.common] + # Ported from SurfaceDuoPkg + AslUpdateLib|Silicon/Qualcomm/QcomPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + + PlatformMemoryMapLib|Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf + PlatformPeiLib|Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.inf + PlatformPrePiLib|Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformPrePiLib.inf + MsPlatformDevicesLib|Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf + SOCSmbiosInfoLib|Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf + +[Components.common] diff --git a/Platform/Qualcomm/sm6225/sm6225.fdf b/Platform/Qualcomm/sm6225/sm6225.fdf new file mode 100644 index 000000000..7a3413144 --- /dev/null +++ b/Platform/Qualcomm/sm6225/sm6225.fdf @@ -0,0 +1,263 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.sm6225_UEFI] +BaseAddress = $(FD_BASE)|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware +Size = $(FD_SIZE)|gArmTokenSpaceGuid.PcdFdSize +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x700 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00700000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +# Apriori +!include Platform/Qualcomm/sm6225/Apriori.fdf.inc + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE +!include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# BSP drivers +!include Platform/Qualcomm/sm6225/dxe.fdf.inc + + # INF Silicon/Qualcomm/sdm845/Drivers/sdm845Dxe/sdm845Dxe.inf // not sdm845 + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + + # + # Helper drivers + # + INF Platform/RenegadePkg/Drivers/SetCPUFreqDxe/SetCPUFreqDxe.inf + + # + # USB Host Support + # + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + + # + # FDT support + # + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + # + # SMBIOS Support + # + INF Platform/RenegadePkg/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf +!ifdef $(INCLUDE_TFTP_COMMAND) + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + INF Platform/EFI_Binaries/Applications/LinuxSimpleMassStorage/LinuxSimpleMassStorage.inf + + # + # Bds + # + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF Platform/RenegadePkg/Drivers/LogoDxe/LogoDxe.inf + + # + # Windows kernel patcher + # + INF Platform/RenegadePkg/Drivers/KernelErrataPatcher/KernelErrataPatcher.inf + + # + # Simple Init GUI + # + INF src/main/SimpleInitMain.inf + + INF src/kernelfdt/KernelFdtDxe.inf + +!if $(AB_SLOTS_SUPPORT) == TRUE + INF GPLDrivers/Drivers/BootSlotDxe/BootSlotDxe.inf + INF GPLDrivers/Application/SwitchSlotsApp/SwitchSlotsApp.inf +!endif + +!if $(ENABLE_LINUX_UTILS) == 1 + FILE FREEFORM = 4b0364cf-1c5b-47aa-9073-d7b5039ce49b { + SECTION RAW = tools/simpleinit.static.uefi.cfg + SECTION UI = "simpleinit.static.uefi.cfg" + } + + INF Platform/RenegadePkg/Application/Reboot2PayloadApp/Reboot2PayloadApp.inf +!endif + +# Device specific fdf +!include $(DEVICE_DXE_FV_COMPONENTS) + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF Silicon/Qualcomm/QcomPkg/PrePi/PrePi.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + FILE FREEFORM = DDE58710-41CD-4306-DBFB-3FA90BB1D2DD { + SECTION UI = "uefiplat.cfg" + SECTION RAW = Platform/Xiaomi/sm6225/RawFiles/fog/uefiplat.cfg + } + +!include Silicon/Qualcomm/QcomPkg/QcomCommonFdf.inc + + diff --git a/Platform/Qualcomm/sm6375/Apriori.fdf.inc b/Platform/Qualcomm/sm6375/Apriori.fdf.inc new file mode 100644 index 000000000..dbbc0fd5e --- /dev/null +++ b/Platform/Qualcomm/sm6375/Apriori.fdf.inc @@ -0,0 +1,84 @@ +APRIORI DXE { + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/SmemDxe/SmemDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/DALSYSDxe/DALSYSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/HWIODxe/HWIODxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ChipInfoDxe/ChipInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/PlatformInfoDxe/PlatformInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/HALIOMMUDxe/HALIOMMUDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/GLinkDxe/GLinkDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ULogDxe/ULogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/NpaDxe/NpaDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/VcsDxe/VcsDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ClockDxe/ClockDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ShmBridgeDxe/ShmBridgeDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6375/TzDxe/ScmDxeLA.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/SdccDxe/SdccDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UFSDxe/UFSDxe.inf + + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/TzDxe/TzDxeLA.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/QcomWDogDxe/QcomWDogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/TLMMDxe/TLMMDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/SPMIDxe/SPMIDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ResetRuntimeDxe/ResetRuntimeDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/PmicDxe/PmicDxeLa.inf + INF Platform/EFI_Binaries/Drivers/sm6375/PILDxe/PILDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/FontDxe/FontDxe.inf + + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/I2CDxe/I2CDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/AdcDxe/AdcDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/QcomChargerDxe/QcomChargerDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ChargerExDxe/ChargerExDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbConfigDxe/UsbConfigDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/TsensDxe/TsensDxe.inf + + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/GpiDxe/GpiDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/DDRInfoDxe/DDRInfoDxe.inf + + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf +} \ No newline at end of file diff --git a/Platform/Qualcomm/sm6375/dxe.fdf.inc b/Platform/Qualcomm/sm6375/dxe.fdf.inc new file mode 100644 index 000000000..676564ad2 --- /dev/null +++ b/Platform/Qualcomm/sm6375/dxe.fdf.inc @@ -0,0 +1,42 @@ + INF Platform/EFI_Binaries/Drivers/sm6375/TzDxe/ScmDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6375/TzDxe/TzDxeLA.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/FontDxe/FontDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/QcomWDogDxe/QcomWDogDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/ChipInfoDxe/ChipInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/GLinkDxe/GLinkDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/SmemDxe/SmemDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ULogDxe/ULogDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/NpaDxe/NpaDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/DALSYSDxe/DALSYSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/VcsDxe/VcsDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ClockDxe/ClockDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/HALIOMMUDxe/HALIOMMUDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/HWIODxe/HWIODxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/GpiDxe/GpiDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/I2CDxe/I2CDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/SPMIDxe/SPMIDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/SdccDxe/SdccDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UFSDxe/UFSDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/TLMMDxe/TLMMDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/PlatformInfoDxe/PlatformInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/PmicDxe/PmicDxeLa.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ChargerExDxe/ChargerExDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/QcomChargerDxe/QcomChargerDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbPwrCtrlDxe/UsbPwrCtrlDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/AdcDxe/AdcDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/TsensDxe/TsensDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/DDRInfoDxe/DDRInfoDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbfnDwc3Dxe/UsbfnDwc3Dxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/UsbMsdDxe/UsbMsdDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbDeviceDxe/UsbDeviceDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/UsbConfigDxe/UsbConfigDxe.inf + + INF Platform/EFI_Binaries/Drivers/sm6375/PILDxe/PILDxe.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ShmBridgeDxe/ShmBridgeDxeLA.inf + INF Platform/EFI_Binaries/Drivers/sm6375/ResetRuntimeDxe/ResetRuntimeDxe.inf \ No newline at end of file diff --git a/Platform/Qualcomm/sm6375/sm6375.dsc b/Platform/Qualcomm/sm6375/sm6375.dsc new file mode 100644 index 000000000..8d39340a3 --- /dev/null +++ b/Platform/Qualcomm/sm6375/sm6375.dsc @@ -0,0 +1,67 @@ +## @file +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. +# Copyright (c) 2018 - 2019, Bingxing Wang. All rights reserved. +# Copyright (c) 2022, Xilin Wu. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ + +[Defines] + SOC_PLATFORM = sm6375 + USE_PHYSICAL_TIMER = TRUE + +!include Silicon/Qualcomm/QcomPkg/QcomCommonDsc.inc + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x40000000 # Starting address + gArmTokenSpaceGuid.PcdSystemMemorySize|0x100000000 + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x5FF8C000 # CPU Vectors + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|19200000 + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|18 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|20 + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|30 + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26 + gArmTokenSpaceGuid.PcdGicDistributorBase|0xf200000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xf300000 + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xf200000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00006225 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x5FF90000 # UEFI Stack + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x00040000 # 256K stack + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 + + gQcomTokenSpaceGuid.PcdUefiMemPoolBase|0x63900000 # DXE Heap base address + gQcomTokenSpaceGuid.PcdUefiMemPoolSize|0x0E000000 # UefiMemorySize, DXE heap size + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x5C000000 + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmPlatformTokenSpaceGuid.PcdClusterCount|2 + + # + # SimpleInit + # + gSimpleInitTokenSpaceGuid.PcdDeviceTreeStore|0x53F00000 + gSimpleInitTokenSpaceGuid.PcdLoggerdUseConsole|FALSE + +[LibraryClasses.common] + # Ported from SurfaceDuoPkg + AslUpdateLib|Silicon/Qualcomm/QcomPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + + PlatformMemoryMapLib|Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf + PlatformPeiLib|Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.inf + PlatformPrePiLib|Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformPrePiLib.inf + MsPlatformDevicesLib|Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf + SOCSmbiosInfoLib|Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf + +[Components.common] diff --git a/Platform/Qualcomm/sm6375/sm6375.fdf b/Platform/Qualcomm/sm6375/sm6375.fdf new file mode 100644 index 000000000..84c724d60 --- /dev/null +++ b/Platform/Qualcomm/sm6375/sm6375.fdf @@ -0,0 +1,263 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.sm6375_UEFI] +BaseAddress = $(FD_BASE)|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware +Size = $(FD_SIZE)|gArmTokenSpaceGuid.PcdFdSize +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x700 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x00700000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +# Apriori +!include Platform/Qualcomm/sm6375/Apriori.fdf.inc + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE +!include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# BSP drivers +!include Platform/Qualcomm/sm6375/dxe.fdf.inc + + # INF Silicon/Qualcomm/sdm845/Drivers/sdm845Dxe/sdm845Dxe.inf // not sdm845 + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + + # + # Helper drivers + # + INF Platform/RenegadePkg/Drivers/SetCPUFreqDxe/SetCPUFreqDxe.inf + + # + # USB Host Support + # + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + + # + # FDT support + # + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + # + # SMBIOS Support + # + INF Platform/RenegadePkg/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf +!ifdef $(INCLUDE_TFTP_COMMAND) + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + INF Platform/EFI_Binaries/Applications/LinuxSimpleMassStorage/LinuxSimpleMassStorage.inf + + # + # Bds + # + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF Platform/RenegadePkg/Drivers/LogoDxe/LogoDxe.inf + + # + # Windows kernel patcher + # + INF Platform/RenegadePkg/Drivers/KernelErrataPatcher/KernelErrataPatcher.inf + + # + # Simple Init GUI + # + INF src/main/SimpleInitMain.inf + + INF src/kernelfdt/KernelFdtDxe.inf + +!if $(AB_SLOTS_SUPPORT) == TRUE + INF GPLDrivers/Drivers/BootSlotDxe/BootSlotDxe.inf + INF GPLDrivers/Application/SwitchSlotsApp/SwitchSlotsApp.inf +!endif + +!if $(ENABLE_LINUX_UTILS) == 1 + FILE FREEFORM = 4b0364cf-1c5b-47aa-9073-d7b5039ce49b { + SECTION RAW = tools/simpleinit.static.uefi.cfg + SECTION UI = "simpleinit.static.uefi.cfg" + } + + INF Platform/RenegadePkg/Application/Reboot2PayloadApp/Reboot2PayloadApp.inf +!endif + +# Device specific fdf +!include $(DEVICE_DXE_FV_COMPONENTS) + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF Silicon/Qualcomm/QcomPkg/PrePi/PrePi.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + + FILE FREEFORM = DDE58710-41CD-4306-DBFB-3FA90BB1D2DD { + SECTION UI = "uefiplat.cfg" + SECTION RAW = Platform/Xiaomi/sm6375/RawFiles/moonstone/uefiplat.cfg + } + +!include Silicon/Qualcomm/QcomPkg/QcomCommonFdf.inc + + diff --git a/Platform/Qualcomm/sm7125/sm7125.fdf b/Platform/Qualcomm/sm7125/sm7125.fdf index 9d3fe0c64..01fcd7339 100644 --- a/Platform/Qualcomm/sm7125/sm7125.fdf +++ b/Platform/Qualcomm/sm7125/sm7125.fdf @@ -31,7 +31,7 @@ ErasePolarity = 1 # This one is tricky, it must be: BlockSize * NumBlocks = Size BlockSize = 0x00001000 -NumBlocks = 0x2000 +NumBlocks = 0x700 ################################################################################ # @@ -49,7 +49,7 @@ NumBlocks = 0x2000 # ################################################################################ -0x00000000|0x02000000 +0x00000000|0x00700000 gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize FV = FVMAIN_COMPACT @@ -208,6 +208,15 @@ READ_LOCK_STATUS = TRUE INF GPLDrivers/Application/SwitchSlotsApp/SwitchSlotsApp.inf !endif +!if $(ENABLE_LINUX_UTILS) == 1 + FILE FREEFORM = 4b0364cf-1c5b-47aa-9073-d7b5039ce49b { + SECTION RAW = tools/simpleinit.static.uefi.cfg + SECTION UI = "simpleinit.static.uefi.cfg" + } + + INF Platform/RenegadePkg/Application/Reboot2PayloadApp/Reboot2PayloadApp.inf +!endif + # Device specific fdf !include $(DEVICE_DXE_FV_COMPONENTS) diff --git a/Platform/Qualcomm/sm8475/Apriori.fdf.inc b/Platform/Qualcomm/sm8475/Apriori.fdf.inc new file mode 100755 index 000000000..ea01259d9 --- /dev/null +++ b/Platform/Qualcomm/sm8475/Apriori.fdf.inc @@ -0,0 +1,205 @@ +APRIORI DXE { + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + +# FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/SmemDxe/SmemDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/SmemDxe/SmemDxe.efi +# SECTION UI = "SmemDxe" +# } +# +# FILE DRIVER = 8E9BD160-B184-11DF-94E2-0800200C9A66 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/DALSys/DALSys.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/DALSys/DALSys.efi +# SECTION UI = "DALSys" +# } +# +# FILE DRIVER = af9763a2-033b-4109-8e17-56a98d380c92 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/HWIODxeDriver/HWIODxeDriver.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/HWIODxeDriver/HWIODxeDriver.efi +# SECTION UI = "HWIODxeDriver" +# } +# +# FILE DRIVER = 10e193df-9966-44e7-b17c-59dd831e20fc { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ChipInfo/ChipInfo.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ChipInfo/ChipInfo.efi +# SECTION UI = "ChipInfo" +# } +# +# FILE DRIVER = B105211B-BBBD-4ADD-A3B0-D1CF4A52154C { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PlatformInfoDxeDriver/PlatformInfoDxeDriver.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PlatformInfoDxeDriver/PlatformInfoDxeDriver.efi +# SECTION UI = "PlatformInfoDxeDriver" +# } +# +# FILE DRIVER = 9A00771F-36D4-4DD5-8916-C48ED9B16B86 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/HALIOMMU/HALIOMMU.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/HALIOMMU/HALIOMMU.efi +# SECTION UI = "HALIOMMU" +# } +# +# FILE DRIVER = E43128A8-8692-42B6-8AFA-676158578D18 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ULogDxe/ULogDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ULogDxe/ULogDxe.efi +# SECTION UI = "ULogDxe" +# } +# +# FILE DRIVER = ABA01FF8-2CCB-4E12-8B2E-CD3F4A742993 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/CmdDbDxe/CmdDbDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/CmdDbDxe/CmdDbDxe.efi +# SECTION UI = "CmdDbDxe" +# } +# +# FILE DRIVER = 0401b830-bff9-44a2-a5f6-95734a33c017 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PwrUtilsDxe/PwrUtilsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PwrUtilsDxe/PwrUtilsDxe.efi +# SECTION UI = "PwrUtilsDxe" +# } +# +# FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219711 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/NpaDxe/NpaDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/NpaDxe/NpaDxe.efi +# SECTION UI = "NpaDxe" +# } +# +# FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219766 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/RpmhDxe/RpmhDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/RpmhDxe/RpmhDxe.efi +# SECTION UI = "RpmhDxe" +# } +# +# FILE DRIVER = 8bd3b475-401a-4b0b-9315-edee61a1eae5 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/VcsDxe/VcsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/VcsDxe/VcsDxe.efi +# SECTION UI = "VcsDxe" +# } +# +# FILE DRIVER = 4DB5DEA6-5302-4D1A-8A82-677A683B0D29 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ClockDxe/ClockDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ClockDxe/ClockDxe.efi +# SECTION UI = "ClockDxe" +# } +# +# // Used to speed up booting. must be loaded after ClockDxe +# INF Platform/RenegadePkg/Drivers/SetCPUFreqDxe/SetCPUFreqDxe.inf +# +# FILE DRIVER = 5824f9de-17d2-4b1f-a5fe-5eb77fa53093 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ICBDxe/ICBDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ICBDxe/ICBDxe.efi +# SECTION UI = "ICBDxe" +# } +# +# FILE DRIVER = 8430c46d-ab1c-4f82-896b-33e156931fb3 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ShmBridgeDxeLA/ShmBridgeDxeLA.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ShmBridgeDxeLA/ShmBridgeDxeLA.efi +# SECTION UI = "ShmBridgeDxeLA" +# } +# +# FILE DRIVER = 4b4973ee-401b-4f36-a6a9-533dfccdfc33 { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ScmDxeLA/ScmDxeLA.efi +# SECTION UI = "ScmDxeLA" +# } +# +# FILE DRIVER = 8681cc5a-0df6-441e-b4b8-e915c538f067 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/DALTLMM/DALTLMM.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/DALTLMM/DALTLMM.efi +# SECTION UI = "DALTLMM" +# } +# +# FILE DRIVER = 2a7b4bef-80cd-49e1-b473-374ba4d673fc { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/SPMI/SPMI.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/SPMI/SPMI.efi +# SECTION UI = "SPMI" +# } +# +# FILE DRIVER = 04DE8591-D2B3-4077-BBBE-B12070094EB6 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/I2C/I2C.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/I2C/I2C.efi +# SECTION UI = "I2C" +# } +# +# FILE DRIVER = 3ae17db7-3cc5-4b89-9304-9549211057ef { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ResetRuntimeDxe/ResetRuntimeDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ResetRuntimeDxe/ResetRuntimeDxe.efi +# SECTION UI = "ResetRuntimeDxe" +# } +# +# FILE DRIVER = 5776232e-082d-4b75-9a0e-fe1d13f7a5d9 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PmicDxe/PmicDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PmicDxe/PmicDxe.efi +# SECTION UI = "PmicDxe" +# } + + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + +# FILE DRIVER = 0d35cd8e-97ea-4f9a-96af-0f0d89f76567 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UFSDxe/UFSDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UFSDxe/UFSDxe.efi +# SECTION UI = "UFSDxe" +# } + + INF FatPkg/EnhancedFatDxe/Fat.inf + +# FILE DRIVER = cf6dfc66-14ab-4e13-84db-9c02912d1404 { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/TzDxeLA/TzDxeLA.efi +# SECTION UI = "TzDxeLA" +# } + + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + +# FILE DRIVER = 7DB0793A-4402-4BE1-906E-D0FABAD2707E { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/DDRInfoDxe/DDRInfoDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/DDRInfoDxe/DDRInfoDxe.efi +# SECTION UI = "DDRInfoDxe" +# } + + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ButtonsDxe/ButtonsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ButtonsDxe/ButtonsDxe.efi +# SECTION UI = "ButtonsDxe" +# } + + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + + + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +} diff --git a/Platform/Qualcomm/sm8475/dxe.fdf.inc b/Platform/Qualcomm/sm8475/dxe.fdf.inc new file mode 100644 index 000000000..ee8b06d7b --- /dev/null +++ b/Platform/Qualcomm/sm8475/dxe.fdf.inc @@ -0,0 +1,211 @@ +// sort alphabetically +# FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ButtonsDxe/ButtonsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ButtonsDxe/ButtonsDxe.efi +# SECTION UI = "ButtonsDxe" +# } +# +# FILE DRIVER = 10e193df-9966-44e7-b17c-59dd831e20fc { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ChipInfo/ChipInfo.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ChipInfo/ChipInfo.efi +# SECTION UI = "ChipInfo" +# } +# +# FILE DRIVER = 4DB5DEA6-5302-4D1A-8A82-677A683B0D29 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ClockDxe/ClockDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ClockDxe/ClockDxe.efi +# SECTION UI = "ClockDxe" +# } +# +# FILE DRIVER = ABA01FF8-2CCB-4E12-8B2E-CD3F4A742993 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/CmdDbDxe/CmdDbDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/CmdDbDxe/CmdDbDxe.efi +# SECTION UI = "CmdDbDxe" +# } +# +# FILE DRIVER = 8E9BD160-B184-11DF-94E2-0800200C9A66 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/DALSys/DALSys.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/DALSys/DALSys.efi +# SECTION UI = "DALSys" +# } +# +# FILE DRIVER = 8681cc5a-0df6-441e-b4b8-e915c538f067 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/DALTLMM/DALTLMM.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/DALTLMM/DALTLMM.efi +# SECTION UI = "DALTLMM" +# } +# +# FILE DRIVER = 7DB0793A-4402-4BE1-906E-D0FABAD2707E { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/DDRInfoDxe/DDRInfoDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/DDRInfoDxe/DDRInfoDxe.efi +# SECTION UI = "DDRInfoDxe" +# } +# +# FILE DRIVER = 9A00771F-36D4-4DD5-8916-C48ED9B16B86 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/HALIOMMU/HALIOMMU.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/HALIOMMU/HALIOMMU.efi +# SECTION UI = "HALIOMMU" +# } +# +# FILE DRIVER = af9763a2-033b-4109-8e17-56a98d380c92 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/HWIODxeDriver/HWIODxeDriver.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/HWIODxeDriver/HWIODxeDriver.efi +# SECTION UI = "HWIODxeDriver" +# } +# +# FILE DRIVER = 5824f9de-17d2-4b1f-a5fe-5eb77fa53093 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ICBDxe/ICBDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ICBDxe/ICBDxe.efi +# SECTION UI = "ICBDxe" +# } +# +# FILE DRIVER = 04DE8591-D2B3-4077-BBBE-B12070094EB6 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/I2C/I2C.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/I2C/I2C.efi +# SECTION UI = "I2C" +# } +# +# FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219711 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/NpaDxe/NpaDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/NpaDxe/NpaDxe.efi +# SECTION UI = "NpaDxe" +# } +# +# FILE DRIVER = B43C22DB-6333-490C-872D-0A73439059FD { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PdcDxe/PdcDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PdcDxe/PdcDxe.efi +# SECTION UI = "PdcDxe" +# } +# +# FILE DRIVER = B105211B-BBBD-4ADD-A3B0-D1CF4A52154C { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PlatformInfoDxeDriver/PlatformInfoDxeDriver.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PlatformInfoDxeDriver/PlatformInfoDxeDriver.efi +# SECTION UI = "PlatformInfoDxeDriver" +# } +# +# FILE DRIVER = 5776232e-082d-4b75-9a0e-fe1d13f7a5d9 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PmicDxe/PmicDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PmicDxe/PmicDxe.efi +# SECTION UI = "PmicDxe" +# } +# +# FILE DRIVER = 0401b830-bff9-44a2-a5f6-95734a33c017 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/PwrUtilsDxe/PwrUtilsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/PwrUtilsDxe/PwrUtilsDxe.efi +# SECTION UI = "PwrUtilsDxe" +# } +# +# FILE DRIVER = 040e1e61-0afb-411b-9ec9-00f3fc59cc13 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/QcomWDogDxe/QcomWDogDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/QcomWDogDxe/QcomWDogDxe.efi +# SECTION UI = "QcomWDogDxe" +# } +# +# FILE DRIVER = 3ae17db7-3cc5-4b89-9304-9549211057ef { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ResetRuntimeDxe/ResetRuntimeDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ResetRuntimeDxe/ResetRuntimeDxe.efi +# SECTION UI = "ResetRuntimeDxe" +# } +# +# FILE DRIVER = CB29F4D1-7F37-4692-A416-93E82E219766 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/RpmhDxe/RpmhDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/RpmhDxe/RpmhDxe.efi +# SECTION UI = "RpmhDxe" +# } +# +# FILE DRIVER = 4b4973ee-401b-4f36-a6a9-533dfccdfc33 { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ScmDxeLA/ScmDxeLA.efi +# SECTION UI = "ScmDxeLA" +# } +# +# FILE DRIVER = 8430c46d-ab1c-4f82-896b-33e156931fb3 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ShmBridgeDxeLA/ShmBridgeDxeLA.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ShmBridgeDxeLA/ShmBridgeDxeLA.efi +# SECTION UI = "ShmBridgeDxeLA" +# } +# +# FILE DRIVER = f541d663-4a48-40aa-aabf-ff158ccae34c { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/SmemDxe/SmemDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/SmemDxe/SmemDxe.efi +# SECTION UI = "SmemDxe" +# } +# +# FILE DRIVER = 2a7b4bef-80cd-49e1-b473-374ba4d673fc { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/SPMI/SPMI.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/SPMI/SPMI.efi +# SECTION UI = "SPMI" +# } +# +# FILE DRIVER = cf6dfc66-14ab-4e13-84db-9c02912d1404 { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/TzDxeLA/TzDxeLA.efi +# SECTION UI = "TzDxeLA" +# } +# +# FILE DRIVER = 0d35cd8e-97ea-4f9a-96af-0f0d89f76567 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UFSDxe/UFSDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UFSDxe/UFSDxe.efi +# SECTION UI = "UFSDxe" +# } +# +# FILE DRIVER = E43128A8-8692-42B6-8AFA-676158578D18 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/ULogDxe/ULogDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/ULogDxe/ULogDxe.efi +# SECTION UI = "ULogDxe" +# } +# +# FILE DRIVER = 8bd3b475-401a-4b0b-9315-edee61a1eae5 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/VcsDxe/VcsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/VcsDxe/VcsDxe.efi +# SECTION UI = "VcsDxe" +# } +# +# FILE DRIVER = beb12bee-f6e1-11e1-9fb8-6c626de4aeb1 { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/XhciPciEmulation/XhciPciEmulation.efi +# SECTION UI = "XhciPciEmulation" +# } +# +# FILE DRIVER = b7f50e91-a759-412c-ade4-dcd03e7f7c28 { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/XhciDxe/XhciDxe.efi +# SECTION UI = "XhciDxe" +# } +# +# FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi +# SECTION UI = "UsbPwrCtrlDxe" +# } +# +# FILE DRIVER = 94f8a6a7-dc34-4101-88c1-99179cceae83 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UsbfnDwc3Dxe/UsbfnDwc3Dxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbfnDwc3Dxe/UsbfnDwc3Dxe.efi +# SECTION UI = "UsbfnDwc3Dxe" +# } +# +# FILE DRIVER = 2d2e62cf-9ecf-43b7-8219-94e7fc713dfe { +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbKbDxe/UsbKbDxe.efi +# SECTION UI = "UsbKbDxe" +# } +# +# FILE DRIVER = cd823a4d-7dec-4531-ae5d-4134fa4127b8 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UsbConfigDxe/UsbConfigDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbConfigDxe/UsbConfigDxe.efi +# SECTION UI = "UsbConfigDxe" +# } +# +# FILE DRIVER = 0A134F0E-075E-40B3-9C63-3B3906804663 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UsbInitDxe/UsbInitDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbInitDxe/UsbInitDxe.efi +# SECTION UI = "UsbInitDxe" +# } +# +# FILE DRIVER = 3299a266-15f0-4346-8318-716336736d3e { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UsbDeviceDxe/UsbDeviceDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbDeviceDxe/UsbDeviceDxe.efi +# SECTION UI = "UsbDeviceDxe" +# } +# +# FILE DRIVER = 5AF77F10-90DF-4E7E-8325-A17EC09D5443 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8550/UsbMsdDxe/UsbMsdDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8550/UsbMsdDxe/UsbMsdDxe.efi +# SECTION UI = "UsbMsdDxe" +# } diff --git a/Platform/Qualcomm/sm8475/sm8475.dsc b/Platform/Qualcomm/sm8475/sm8475.dsc new file mode 100644 index 000000000..6f3319fee --- /dev/null +++ b/Platform/Qualcomm/sm8475/sm8475.dsc @@ -0,0 +1,66 @@ +## @file +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. +# Copyright (c) 2018 - 2019, Bingxing Wang. All rights reserved. +# Copyright (c) 2022, Xilin Wu. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +################################################################################ +# +# Defines Section - statements that will be processed to create a Makefile. +# +################################################################################ + +[Defines] + SOC_PLATFORM = SM8475 + USE_PHYSICAL_TIMER = FALSE + +!include Silicon/Qualcomm/QcomPkg/QcomCommonDsc.inc + +[PcdsFixedAtBuild.common] + gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000 # Starting address + gArmTokenSpaceGuid.PcdSystemMemorySize|0xFDFA0000 # Limit to 4GB Size here + + gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xA7600000 # CPU Vectors + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|19200000 + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29 + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30 + gArmTokenSpaceGuid.PcdGicDistributorBase|0x17100000 + gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x17180000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000850 + gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x9F590000 # UEFI Stack + gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x00040000 # 256K stack + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|44 + + gQcomTokenSpaceGuid.PcdUefiMemPoolBase|0xA0000000 # DXE Heap base address + gQcomTokenSpaceGuid.PcdUefiMemPoolSize|0x0EB00000 # UefiMemorySize, DXE heap size + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0xB8000000 + + gArmPlatformTokenSpaceGuid.PcdCoreCount|8 + gArmPlatformTokenSpaceGuid.PcdClusterCount|3 + + # + # SimpleInit + # + gSimpleInitTokenSpaceGuid.PcdDeviceTreeStore|0x83300000 + gSimpleInitTokenSpaceGuid.PcdLoggerdUseConsole|FALSE + +[LibraryClasses.common] + + # Ported from SurfaceDuoPkg + AslUpdateLib|Silicon/Qualcomm/QcomPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf + + PlatformMemoryMapLib|Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf + PlatformPeiLib|Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.inf + PlatformPrePiLib|Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformPrePiLib.inf + MsPlatformDevicesLib|Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf + SOCSmbiosInfoLib|Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf + +[Components.common] + diff --git a/Platform/Qualcomm/sm8475/sm8475.fdf b/Platform/Qualcomm/sm8475/sm8475.fdf new file mode 100644 index 000000000..6786ea89b --- /dev/null +++ b/Platform/Qualcomm/sm8475/sm8475.fdf @@ -0,0 +1,248 @@ +# +# Copyright (c) 2018, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# + +################################################################################ +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +################################################################################ + +[FD.sm8475_UEFI] +BaseAddress = $(FD_BASE)|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware +Size = $(FD_SIZE)|gArmTokenSpaceGuid.PcdFdSize +ErasePolarity = 1 + +# This one is tricky, it must be: BlockSize * NumBlocks = Size +BlockSize = 0x00001000 +NumBlocks = 0x2000 + +################################################################################ +# +# Following are lists of FD Region layout which correspond to the locations of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by +# the pipe "|" character, followed by the size of the region, also in hex with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# +################################################################################ + +0x00000000|0x02000000 +gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize +FV = FVMAIN_COMPACT + +################################################################################ +# +# FV Section +# +# [FV] section is used to define what components or modules are placed within a flash +# device file. This section also defines order the components and modules are positioned +# within the image. The [FV] section consists of define statements, set statements and +# module statements. +# +################################################################################ + +[FV.FvMain] +BlockSize = 0x40 +NumBlocks = 0 # This FV gets compressed so make it just big enough +FvAlignment = 8 # FV alignment and FV attributes setting. +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + +# Apriori +!include Platform/Qualcomm/sm8475/Apriori.fdf.inc + + INF MdeModulePkg/Core/Dxe/DxeMain.inf + + # + # PI DXE Drivers producing Architectural Protocols (EFI Services) + # + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + +!if $(SECURE_BOOT_ENABLE) == TRUE +!include ArmPlatformPkg/SecureBootDefaultKeys.fdf.inc + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf + INF SecurityPkg/EnrollFromDefaultKeysApp/EnrollFromDefaultKeysApp.inf + INF SecurityPkg/VariableAuthenticated/SecureBootDefaultKeysDxe/SecureBootDefaultKeysDxe.inf +!endif + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf + INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf + INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf + INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf + + # + # Multiple Console IO support + # + INF EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf + INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf + + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + +# BSP drivers +!include Platform/Qualcomm/sm8475/dxe.fdf.inc + + # INF Silicon/Qualcomm/sm8475/Drivers/sm8475Dxe/sm8475Dxe.inf + INF Silicon/Qualcomm/QcomPkg/Drivers/SimpleFbDxe/SimpleFbDxe.inf + + # + # Helper drivers + # + INF Platform/RenegadePkg/Drivers/SetCPUFreqDxe/SetCPUFreqDxe.inf + + # + # USB Host Support + # + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + # + # FAT filesystem + GPT/MBR partitioning + # + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF FatPkg/EnhancedFatDxe/Fat.inf + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf + + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + + # + # ACPI Support + # + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf + INF MdeModulePkg/Universal/Acpi/BootGraphicsResourceTableDxe/BootGraphicsResourceTableDxe.inf + # INF RuleOverride = ACPITABLE sm8475Pkg/AcpiTables/AcpiTables.inf + + # + # FDT support + # + INF EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf + + # + # SMBIOS Support + # + INF Platform/RenegadePkg/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # UEFI applications + # + INF ShellPkg/Application/Shell/Shell.inf +!ifdef $(INCLUDE_TFTP_COMMAND) + INF ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf +!endif #$(INCLUDE_TFTP_COMMAND) + + INF Platform/EFI_Binaries/Applications/LinuxSimpleMassStorage/LinuxSimpleMassStorage.inf + + # + # Bds + # + INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DriverHealthManagerDxe/DriverHealthManagerDxe.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + INF MdeModulePkg/Application/UiApp/UiApp.inf + INF Platform/RenegadePkg/Drivers/LogoDxe/LogoDxe.inf + + # + # Windows kernel patcher + # + INF Platform/RenegadePkg/Drivers/KernelErrataPatcher/KernelErrataPatcher.inf + + # + # Simple Init GUI + # + INF src/main/SimpleInitMain.inf + + INF src/kernelfdt/KernelFdtDxe.inf + +!if $(AB_SLOTS_SUPPORT) == TRUE + INF GPLDrivers/Drivers/BootSlotDxe/BootSlotDxe.inf + INF GPLDrivers/Application/SwitchSlotsApp/SwitchSlotsApp.inf +!endif + +# Device specific fdf +!include $(DEVICE_DXE_FV_COMPONENTS) + +[FV.FVMAIN_COMPACT] +FvAlignment = 8 +ERASE_POLARITY = 1 +MEMORY_MAPPED = TRUE +STICKY_WRITE = TRUE +LOCK_CAP = TRUE +LOCK_STATUS = TRUE +WRITE_DISABLED_CAP = TRUE +WRITE_ENABLED_CAP = TRUE +WRITE_STATUS = TRUE +WRITE_LOCK_CAP = TRUE +WRITE_LOCK_STATUS = TRUE +READ_DISABLED_CAP = TRUE +READ_ENABLED_CAP = TRUE +READ_STATUS = TRUE +READ_LOCK_CAP = TRUE +READ_LOCK_STATUS = TRUE + + INF Silicon/Qualcomm/QcomPkg/PrePi/PrePi.inf + + FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { + SECTION FV_IMAGE = FVMAIN + } + } + +!include Silicon/Qualcomm/QcomPkg/QcomCommonFdf.inc + + diff --git a/Platform/SHIFT/sdm845/FdtBlob/sdm845-shift-axolotl.dtb b/Platform/SHIFT/sdm845/FdtBlob/sdm845-shift-axolotl.dtb new file mode 100644 index 000000000..1535434c6 Binary files /dev/null and b/Platform/SHIFT/sdm845/FdtBlob/sdm845-shift-axolotl.dtb differ diff --git a/Platform/SHIFT/sdm845/FdtBlob_compat/axolotl.dtb b/Platform/SHIFT/sdm845/FdtBlob_compat/axolotl.dtb new file mode 100644 index 000000000..f08b07fba Binary files /dev/null and b/Platform/SHIFT/sdm845/FdtBlob_compat/axolotl.dtb differ diff --git a/Platform/SHIFT/sdm845/axolotl.dsc b/Platform/SHIFT/sdm845/axolotl.dsc new file mode 100644 index 000000000..1af248b69 --- /dev/null +++ b/Platform/SHIFT/sdm845/axolotl.dsc @@ -0,0 +1,32 @@ +[Defines] + VENDOR_NAME = SHIFT + PLATFORM_NAME = axolotl + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sdm845/sdm845.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/SHIFT/sdm845/axolotl.fdf.inc + + # Enable A/B Slot Environment + AB_SLOTS_SUPPORT = TRUE + +!include Platform/Qualcomm/sdm845/sdm845.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DAB_SLOTS_SUPPORT=1 -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2160 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|402 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"SHIFT" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"SHIFT6mq" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"axolotl" diff --git a/Platform/SHIFT/sdm845/axolotl.fdf.inc b/Platform/SHIFT/sdm845/axolotl.fdf.inc new file mode 100644 index 000000000..5beb10d83 --- /dev/null +++ b/Platform/SHIFT/sdm845/axolotl.fdf.inc @@ -0,0 +1,24 @@ +// per-device BSP DXEs +//sdm845 ButtonsDxe only work for first touch, polaris one works well +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sdm845/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/polaris/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +// ACPI Tables +//FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { +// SECTION RAW = Silicon/Qualcomm/sdm845/AcpiTables/DBG2.aml +// SECTION RAW = Platform/SHIFT/sdm845/AcpiTables/axolotl/DSDT.aml +// SECTION RAW = Silicon/Qualcomm/sdm845/AcpiTables/MADT.aml +// SECTION RAW = Silicon/Qualcomm/sdm845/AcpiTables/FADT.aml +// SECTION RAW = Silicon/Qualcomm/sdm845/AcpiTables/GTDT.aml +// SECTION RAW = Silicon/Qualcomm/sdm845/AcpiTables/IORT.aml +// SECTION RAW = Silicon/Qualcomm/sdm845/AcpiTables/PPTT.aml +// SECTION UI = "AcpiTables" +//} + +// Mainline device tree blob +FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/SHIFT/sdm845/FdtBlob/sdm845-shift-axolotl.dtb +} diff --git a/Platform/Samsung/sdm845/FdtBlob_compat/starqlte.dtb b/Platform/Samsung/sdm845/FdtBlob_compat/starqlte.dtb new file mode 100644 index 000000000..bf8b17807 Binary files /dev/null and b/Platform/Samsung/sdm845/FdtBlob_compat/starqlte.dtb differ diff --git a/Platform/Samsung/sdm845/starqlte.dsc b/Platform/Samsung/sdm845/starqlte.dsc new file mode 100644 index 000000000..6564e0542 --- /dev/null +++ b/Platform/Samsung/sdm845/starqlte.dsc @@ -0,0 +1,29 @@ +[Defines] + VENDOR_NAME = Samsung + PLATFORM_NAME = starqlte + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sdm845/sdm845.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Samsung/sdm845/starqlte.fdf.inc + +!include Platform/Qualcomm/sdm845/sdm845.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1440 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2960 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|400 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Samsung" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Galaxy S9" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"starqlte" diff --git a/Platform/Samsung/sdm845/starqlte.fdf.inc b/Platform/Samsung/sdm845/starqlte.fdf.inc new file mode 100644 index 000000000..b9b31d275 --- /dev/null +++ b/Platform/Samsung/sdm845/starqlte.fdf.inc @@ -0,0 +1,8 @@ +// per-device BSP DXEs + +// ACPI Tables + +// Mainline device tree blob + +// We do not have a mainline port for starqlte yet so linux simple mass storage remains as untested + diff --git a/Platform/Samsung/sm7150/FdtBlob_compat/a71.dtb b/Platform/Samsung/sm7150/FdtBlob_compat/a71.dtb new file mode 100644 index 000000000..2dc552bf1 Binary files /dev/null and b/Platform/Samsung/sm7150/FdtBlob_compat/a71.dtb differ diff --git a/Platform/Samsung/sm7150/a71.dsc b/Platform/Samsung/sm7150/a71.dsc new file mode 100644 index 000000000..15d39bec2 --- /dev/null +++ b/Platform/Samsung/sm7150/a71.dsc @@ -0,0 +1,29 @@ +[Defines] + VENDOR_NAME = Samsung + PLATFORM_NAME = a71 + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm7150/sm7150.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Samsung/sm7150/a71.fdf.inc + +!include Platform/Qualcomm/sm7150/sm7150.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2400 + # gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9c400000 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|350 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Samsung" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Galaxy A71" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"a71" diff --git a/Platform/Samsung/sm7150/a71.fdf.inc b/Platform/Samsung/sm7150/a71.fdf.inc new file mode 100644 index 000000000..4b78b3cf1 --- /dev/null +++ b/Platform/Samsung/sm7150/a71.fdf.inc @@ -0,0 +1,5 @@ +// per-device BSP DXEs + +//FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + //SECTION RAW = Platform/Samsung/sm7150/FdtBlob/a71.dtb +//} diff --git a/Platform/Samsung/sm8150/AcpiTables/winner/DSDT.aml b/Platform/Samsung/sm8150/AcpiTables/winner/DSDT.aml new file mode 100644 index 000000000..27d2f0f96 Binary files /dev/null and b/Platform/Samsung/sm8150/AcpiTables/winner/DSDT.aml differ diff --git a/Platform/Samsung/sm8150/FdtBlob/sm8150-Samsung-winner.dtb b/Platform/Samsung/sm8150/FdtBlob/sm8150-Samsung-winner.dtb new file mode 100644 index 000000000..dcdb6119a Binary files /dev/null and b/Platform/Samsung/sm8150/FdtBlob/sm8150-Samsung-winner.dtb differ diff --git a/Platform/Samsung/sm8150/winner.dsc b/Platform/Samsung/sm8150/winner.dsc new file mode 100644 index 000000000..5bd6663ff --- /dev/null +++ b/Platform/Samsung/sm8150/winner.dsc @@ -0,0 +1,30 @@ +[Defines] + VENDOR_NAME = Samsung + PLATFORM_NAME = winner + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8150/sm8150.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Samsung/sm8150/winner.fdf.inc + +!include Platform/Qualcomm/sm8150/sm8150.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|2152 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|1536 + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress|0x9c400000 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|394 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Samsung" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Galaxy Fold" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"winner" diff --git a/Platform/Samsung/sm8150/winner.fdf.inc b/Platform/Samsung/sm8150/winner.fdf.inc new file mode 100644 index 000000000..bc00d97fa --- /dev/null +++ b/Platform/Samsung/sm8150/winner.fdf.inc @@ -0,0 +1,51 @@ +// per-device BSP DXEs +FILE DRIVER = 8e9bd160-b184-11df-94e2-0800200c9a66 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/DALSys/DALSys.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/winner/DALSys/DALSys.efi + SECTION UI = "DALSys" +} + +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/winner/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} +FILE DRIVER = f10f76db-42c1-533f-34a8-69be24653110 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/SdccDxe/SdccDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/SdccDxe/SdccDxe.efi + SECTION UI = "SdccDxe" + } + +FILE DRIVER = 11faed4c-b21f-4d88-8e48-c4c28a1e50df { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/sm8150/WP_Binaries/UsbPwrCtrlDxe/UsbPwrCtrlDxe.efi + SECTION UI = "UsbPwrCtrlDxe" +} + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { +# Customized DSDT + SECTION RAW = Platform/Samsung/sm8150/AcpiTables/winner/DSDT.aml +# Common Tables + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/APIC.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BERT.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/BGRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FACP.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/FPDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/IORT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MCFG.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/MSDM.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/PPTT.aml + SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/TPM2.aml +# SECTION RAW = Silicon/Qualcomm/sm8150/AcpiTables/BuiltIn/XSDT.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob +//FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + //SECTION RAW = Platform/Samsung/sm8150/FdtBlob/winner/sm8150-Samsung-winner.dtb +//} + diff --git a/Platform/Samsung/sm8550/FdtBlob_compat/dm1q.dtb b/Platform/Samsung/sm8550/FdtBlob_compat/dm1q.dtb new file mode 100644 index 000000000..d4feabfed Binary files /dev/null and b/Platform/Samsung/sm8550/FdtBlob_compat/dm1q.dtb differ diff --git a/Platform/Samsung/sm8550/dm1q.dsc b/Platform/Samsung/sm8550/dm1q.dsc new file mode 100644 index 000000000..87f565035 --- /dev/null +++ b/Platform/Samsung/sm8550/dm1q.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Samsung + PLATFORM_NAME = dm1q + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8550/sm8550.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Samsung/sm8550/dm1q.fdf.inc + +!include Platform/Qualcomm/sm8550/sm8550.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2340 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|480 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Samsung" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Galaxy S23" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"dm1q" diff --git a/Platform/Samsung/sm8550/dm1q.fdf.inc b/Platform/Samsung/sm8550/dm1q.fdf.inc new file mode 100644 index 000000000..f93ab8f24 --- /dev/null +++ b/Platform/Samsung/sm8550/dm1q.fdf.inc @@ -0,0 +1,24 @@ +// per-device BSP DXEs +# FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/Devices/dm1q/ButtonsDxe/ButtonsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/dm1q/ButtonsDxe/ButtonsDxe.efi +# SECTION UI = "ButtonsDxe" +# } + +// ACPI Tables +# FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { +# SECTION RAW = Silicon/Qualcomm/sm8550/AcpiTables/DBG2.aml +# SECTION RAW = Platform/Samsung/sm8550/AcpiTables/dm1q/DSDT.AML +# SECTION RAW = Silicon/Qualcomm/sm8550/AcpiTables/MADT.aml +# SECTION RAW = Silicon/Qualcomm/sm8550/AcpiTables/FADT.aml +# SECTION RAW = Silicon/Qualcomm/sm8550/AcpiTables/GTDT.aml +# SECTION RAW = Silicon/Qualcomm/sm8550/AcpiTables/IORT.aml +# SECTION RAW = Silicon/Qualcomm/sm8550/AcpiTables/PPTT.aml +# SECTION UI = "AcpiTables" +# } + +// Mainline device tree blob +# FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { +# SECTION RAW = Platform/Qualcomm/sm8550/FdtBlob/sm8550-generic-msd.dtb +# } + diff --git a/Platform/Xiaomi/sdm660/FdtBlob_compat/nitrogen.dtb b/Platform/Xiaomi/sdm660/FdtBlob_compat/nitrogen.dtb new file mode 100755 index 000000000..3e53f8459 Binary files /dev/null and b/Platform/Xiaomi/sdm660/FdtBlob_compat/nitrogen.dtb differ diff --git a/Platform/Xiaomi/sdm660/nitrogen.dsc b/Platform/Xiaomi/sdm660/nitrogen.dsc new file mode 100644 index 000000000..3807907ad --- /dev/null +++ b/Platform/Xiaomi/sdm660/nitrogen.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = nitrogen + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sdm660/sdm660.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sdm660/nitrogen.fdf.inc + +!include Platform/Qualcomm/sdm660/sdm660.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2160 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|350 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Mi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Max 3" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"nitrogen" diff --git a/Platform/Xiaomi/sdm660/nitrogen.fdf.inc b/Platform/Xiaomi/sdm660/nitrogen.fdf.inc new file mode 100644 index 000000000..1717f68ba --- /dev/null +++ b/Platform/Xiaomi/sdm660/nitrogen.fdf.inc @@ -0,0 +1,16 @@ +// per-device BSP DXEs + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/DSDT/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/FACS.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/FADT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/MADT.aml + SECTION RAW = Silicon/Qualcomm/sdm660/AcpiTables/BuiltIn/MCFG.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml new file mode 100644 index 000000000..55d210163 Binary files /dev/null and b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml differ diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.dsl new file mode 100644 index 000000000..35857ed9d --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.dsl @@ -0,0 +1,99 @@ +DefinitionBlock ("", "DSDT", 2, "QCOMM ", "SM6225 ", 0x00000003) +{ + Scope (_SB) + { + Name (PSUB, "MTP06225") + Name (SOID, 0xFFFFFFFF) + Name (STOR, 0xABCABCAB) + Name (SIDS, "899800000000000") + Name (SIDV, 0xFFFFFFFF) + Name (SVMJ, 0xFFFF) + Name (SVMI, 0xFFFF) + Name (SDFE, 0xFFFF) + Name (SFES, "899800000000000") + Name (SIDM, 0x0000000FFFFFFFFF) + Name (SUFS, 0xFFFFFFFF) + Name (PUS3, 0xFFFFFFFF) + Name (SUS3, 0xFFFFFFFF) + Name (SIDT, 0xFFFFFFFF) + Name (SOSN, 0xAAAAAAAABBBBBBBB) + Name (PLST, 0xFFFFFFFF) + Name (EMUL, 0xFFFFFFFF) + Name (SJTG, 0xFFFFFFFF) + Name (RMTB, 0xAAAAAAAA) + Name (RMTX, 0xBBBBBBBB) + Name (RFMB, 0xCCCCCCCC) + Name (RFMS, 0xDDDDDDDD) + Name (RFAB, 0xEEEEEEEE) + Name (RFAS, 0x77777777) + Name (TCMA, 0xDEADBEEF) + Name (TCML, 0xBEEFDEAD) + Name (SOSI, 0xDEADBEEFFFFFFFFF) + Name (PRP0, 0xFFFFFFFF) + Name (PRP1, 0xFFFFFFFF) + Name (PRP2, 0xFFFFFFFF) + Name (PRP3, 0xFFFFFFFF) + Name (PRP4, 0xFFFFFFFF) + Name (PRP5, 0xFFFFFFFF) + Name (PRP6, 0xFFFFFFFF) + + Device (UFS0) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_HID, "QCOM24A5") // _HID: Hardware ID + Alias (^EMUL, EMUL) + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x04804000, // Address Base + 0x00014000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000184, + } + }) + Return (RBUF) /* \_SB_.UFS0._CRS.RBUF */ + } + + Device (DEV0) + { + Method (_ADR, 0, NotSerialized) // _ADR: Address + { + Return (0x08) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + } + } + + Include("abd.dsl") + + Include("pmic_core.dsl") + + Include("scm.dsl"); + + Include("spmi.dsl"); + + Include("qcgpio.dsl"); + + Include("btns.dsl"); + + Include("pep_lpi.dsl"); + + Include("usb.dsl"); + + } +} + diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/abd.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/abd.dsl new file mode 100644 index 000000000..e8762357b --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/abd.dsl @@ -0,0 +1,20 @@ +Device (ABD) +{ + Name (_HID, "QCOM0527") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (ROP1, GenericSerialBus, Zero, 0x0100) + Name (AVBL, Zero) + Alias (PSUB, _SUB) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If ((Arg0 == 0x09)) + { + AVBL = Arg1 + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xF) + } +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/btns.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/btns.dsl new file mode 100644 index 000000000..6f1295bbe --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/btns.dsl @@ -0,0 +1,74 @@ +Device (BTNS) +{ + Name (_HID, "ACPI0011" /* Generic Buttons Device */) // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullDown, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0000 + } + GpioInt (Edge, ActiveBoth, Exclusive, PullUp, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0085 + } + GpioInt (Edge, ActiveBoth, Exclusive, PullDown, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0001 + } + }) + Return (RBUF) /* \_SB_.BTNS._CRS.RBUF */ + } + + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("fa6bd625-9ce8-470d-a2c7-b3ca36c4282e") /* Generic Buttons Device */, + Package (0x04) + { + Package (0x05) // Portable Device Control + { + Zero, + One, + Zero, + One, + 0x0D + }, + + Package (0x05) // Power + { + One, + Zero, + One, + One, + 0x81 + }, + + Package (0x05) // Vol Up + { + One, + One, + One, + 0x0C, + 0xE9 + }, + + Package (0x05) // Vol Down + { + One, + 0x02, + One, + 0x0C, + 0xEA + } + } + }) +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/gpio.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/gpio.dsl new file mode 100644 index 000000000..533a449b3 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/gpio.dsl @@ -0,0 +1,90 @@ + Device (GIO0) + { + Name (_HID, "QCOM050D") // _HID: Hardware ID + Name (_CID, "QCOMFFE3") // _CID: Compatible ID + Name (_UID, Zero) // _UID: Unique ID + Alias (\_SB.PSUB, _SUB) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00400000, // Address Base + 0x00C00000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000249, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, ) + { + 0x0000025B, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000259, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x0000022C, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x0000024E, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000292, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000239, + } + }) + Return (RBUF) /* \_SB_.GIO0._CRS.RBUF */ + } + + Method (OFNI, 0, NotSerialized) + { + Name (RBUF, Buffer (0x02) + { + 0xAF, 0x00 // .. + }) + Return (RBUF) /* \_SB_.GIO0.OFNI.RBUF */ + } + + Name (GABL, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If ((Arg0 == 0x08)) + { + GABL = Arg1 + } + } + + Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts + { + GpioInt (Edge, ActiveHigh, Exclusive, PullDown, 0x01F4, + "\\_SB.GIO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x00BD + } + }) + Method (_EBD, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.GPU0, 0x92) // Device-Specific + } + } \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/pep_lpi.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/pep_lpi.dsl new file mode 100644 index 000000000..8884bbe03 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/pep_lpi.dsl @@ -0,0 +1,1680 @@ + Device (SYSM) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x00100000) // _UID: Unique ID + Device (APC0) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x0100) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x02000000, + 0x03, + Package (0x0A) + { + 0x0BB8, + 0x044C, + One, + Zero, + Zero, + Zero, + 0x0400, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "CCI.E3" + }, + + Package (0x0A) + { + 0x0DAC, + 0x047E, + One, + Zero, + Zero, + Zero, + 0x0500, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "CCI.E3+RPM" + }, + + Package (0x0A) + { + 0x80E8, + 0x01F4, + One, + 0x20, + Zero, + Zero, + 0x0300, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "platform.xo" + } + }) + Device (CL0) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x01000000, + 0x03, + Package (0x0A) + { + 0x012C, + 0x82, + Zero, + Zero, + Zero, + Zero, + 0x20, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D2d" + }, + + Package (0x0A) + { + 0x015E, + 0x96, + Zero, + Zero, + Zero, + Zero, + 0x30, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D2e" + }, + + Package (0x0A) + { + 0x1900, + 0x0384, + One, + Zero, + Zero, + 0x03, + 0x40, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D4" + } + }) + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C3_NI" + } + }) + } + + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C3_NI" + } + }) + } + + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C3_NI" + } + }) + } + + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C3_NI" + } + }) + } + } + + Device (CL1) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x20) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x01000000, + 0x03, + Package (0x0A) + { + 0x0384, + 0xC8, + Zero, + Zero, + Zero, + Zero, + 0x20, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D2d" + }, + + Package (0x0A) + { + 0x03E8, + 0x0190, + Zero, + Zero, + Zero, + Zero, + 0x30, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D2e" + }, + + Package (0x0A) + { + 0x1770, + 0x04B0, + One, + Zero, + Zero, + 0x03, + 0x40, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D4" + } + }) + Device (CPU4) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C3_NI" + } + }) + } + + Device (CPU5) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C3_NI" + } + }) + } + + Device (CPU6) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C3_NI" + } + }) + } + + Device (CPU7) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C3_NI" + } + }) + } + } + } + } diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/pmic_core.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/pmic_core.dsl new file mode 100644 index 000000000..89a2efbb5 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/pmic_core.dsl @@ -0,0 +1,200 @@ +Device (PMIC) +{ + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + SPMI + }) + Name (_HID, "QCOM052E") // _HID: Hardware ID + Name (_CID, "PNP0CA3") // _CID: Compatible ID + Alias (PSUB, _SUB) + Method (PMCF, 0, NotSerialized) + { + Name (CFG0, Package (0x04) + { + 0x02, + Package (0x02) + { + Zero, + One + }, + + Package (0x02) + { + 0x02, + 0x03 + } + }) + Return (CFG0) /* \_SB_.PMIC.PMCF.CFG0 */ + } +} + +Device (PM01) +{ + Name (_HID, "QCOM0530") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, One) // _UID: Unique ID + Name (_DEP, Package (One) // _DEP: Dependencies + { + PMIC + }) + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x000000D7, + } + }) + Return (RBUF) /* \_SB_.PM01._CRS.RBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + While (One) + { + Name (_T_0, Buffer (0x01) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z + { + 0x00 // . + }) + CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.PM01._DSM._T_0 */ + If ((_T_0 == ToUUID ("4f248f40-d5e2-499f-834c-27758ea1cd3f") /* GPIO Controller */)) + { + While (One) + { + Name (_T_1, 0x00) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z + _T_1 = ToInteger (Arg2) + If ((_T_1 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + ElseIf ((_T_1 == One)) + { + Return (Package (0x02) + { + Zero, + One + }) + } + Else + { + } + + Break + } + } + Else + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Break + } + } +} + +Device (PMAP) +{ + Name (_HID, "QCOM052F") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_DEP, Package (0x03) // _DEP: Dependencies + { + PMIC, + ABD, + SCM0 + }) + Method (GEPT, 0, NotSerialized) + { + Name (BUFF, Buffer (0x04){}) + CreateByteField (BUFF, Zero, STAT) + CreateWordField (BUFF, 0x02, DATA) + DATA = 0x02 + Return (DATA) /* \_SB_.PMAP.GEPT.DATA */ + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, Buffer (0x02) + { + 0x79, 0x00 // y. + }) + Return (RBUF) /* \_SB_.PMAP._CRS.RBUF */ + } +} + +Device (PRTC) +{ + Name (_HID, "ACPI000E" /* Time and Alarm Device */) // _HID: Hardware ID + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + PMAP + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_GCP, 0, NotSerialized) // _GCP: Get Capabilities + { + Return (0x04) + } + + Field (\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + Connection ( + I2cSerialBusV2 (0x0002, ControllerInitiated, 0x00000000, + AddressingMode7Bit, "\\_SB.ABD", + 0x00, ResourceConsumer, , Exclusive, + ) + ), + AccessAs (BufferAcc, AttribRawBytes (0x18)), + FLD0, 192 + } + + Method (_GRT, 0, NotSerialized) // _GRT: Get Real Time + { + Name (BUFF, Buffer (0x1A){}) + CreateField (BUFF, 0x10, 0x80, TME1) + CreateField (BUFF, 0x90, 0x20, ACT1) + CreateField (BUFF, 0xB0, 0x20, ACW1) + BUFF = FLD0 /* \_SB_.PRTC.FLD0 */ + Return (TME1) /* \_SB_.PRTC._GRT.TME1 */ + } + + Method (_SRT, 1, NotSerialized) // _SRT: Set Real Time + { + Name (BUFF, Buffer (0x32){}) + CreateByteField (BUFF, Zero, STAT) + CreateField (BUFF, 0x10, 0x80, TME1) + CreateField (BUFF, 0x90, 0x20, ACT1) + CreateField (BUFF, 0xB0, 0x20, ACW1) + ACT1 = Zero + TME1 = Arg0 + ACW1 = Zero + BUFF = FLD0 = BUFF /* \_SB_.PRTC._SRT.BUFF */ + If ((STAT != Zero)) + { + Return (One) + } + + Return (Zero) + } +} + +Device (PEXT) +{ + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + SPMI, + PMIC + }) + Name (_HID, "QCOM05CE") // _HID: Hardware ID + Alias (PSUB, _SUB) +} diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/qcgpio.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/qcgpio.dsl new file mode 100644 index 000000000..44067b4d9 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/qcgpio.dsl @@ -0,0 +1,41 @@ +Device (GIO0) +{ + Name (_HID, "QCOM0217") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TLMM register address space + Memory32Fixed (ReadWrite, 0x00400000, 0x00C00000) + + // Summary Interrupt shared by all banks + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {648} // For PDC Wake up ::TLMM GPIo 126 SD Card Detection + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {568} // For PDC Wake up ::TLMM GPIo 54 + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {646} // For PDC Wake up ::TLMM GPIo 124, Hall sensor used for lid + }) + Return (RBUF) + } + // ACPI method to return Num pins + Method(OFNI, 0x0, NotSerialized) { + Name(RBUF, Buffer() + { + 0x96, // 0: TOTAL_GPIO_PINS + 0x00 // 1: TOTAL_GPIO_PINS + }) + Return (RBUF) + } + + Name(GABL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(LEqual(Arg0, 0x8)) + { + Store(Arg1, GABL) + } + } +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/scm.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/scm.dsl new file mode 100644 index 000000000..3c6567239 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/scm.dsl @@ -0,0 +1,6 @@ +Device (SCM0) +{ + Name (_HID, "QCOM050B") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/spmi.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/spmi.dsl new file mode 100644 index 000000000..3550574f0 --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/spmi.dsl @@ -0,0 +1,31 @@ +Device (SPMI) +{ + Name (_HID, "QCOM050C") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_CID, "PNP0CA2") // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x01C00000, // Address Base + 0x02800000, // Address Length + ) + }) + Return (RBUF) /* \_SB_.SPMI._CRS.RBUF */ + } + + Method (CONF, 0, NotSerialized) + { + Name (XBUF, Buffer (0x1A) + { + /* 0000 */ 0x00, 0x01, 0x01, 0x01, 0xFF, 0x00, 0x02, 0x00, // ........ + /* 0008 */ 0x0A, 0x07, 0x04, 0x07, 0x01, 0xFF, 0x10, 0x01, // ........ + /* 0010 */ 0x00, 0x01, 0x01, 0xC0, 0x00, 0x00, 0x02, 0x80, // ...@.... + /* 0018 */ 0x00, 0x00 // .. + }) + Return (XBUF) /* \_SB_.SPMI.CONF.XBUF */ + } +} diff --git a/Platform/Xiaomi/sm6225/AcpiTables/fog/usb.dsl b/Platform/Xiaomi/sm6225/AcpiTables/fog/usb.dsl new file mode 100644 index 000000000..1dbe690fc --- /dev/null +++ b/Platform/Xiaomi/sm6225/AcpiTables/fog/usb.dsl @@ -0,0 +1,416 @@ +Name (QUFN, Zero) + Name (DPP0, Buffer (One) + { + 0x00 // . + }) + Name (DPP1, Buffer (One) + { + 0x00 // . + }) + Name (MPP0, Buffer (One) + { + 0x00 // . + }) + Name (MPP1, Buffer (One) + { + 0x00 // . + }) + Name (HPDB, Zero) + Name (HPDS, Buffer (One) + { + 0x00 // . + }) + Name (PINA, Zero) + Name (DPPN, 0x0D) + Name (CCST, Buffer (One) + { + 0x02 // . + }) + Name (PORT, Buffer (One) + { + 0x02 // . + }) + Name (HIRQ, Buffer (One) + { + 0x00 // . + }) + Name (HSFL, Buffer (One) + { + 0x00 // . + }) + Name (USBC, Buffer (One) + { + 0x0B // . + }) + Name (MUXC, Buffer (One) + { + 0x00 // . + }) + Device (URS0) + { + Method (URSI, 0, NotSerialized) + { + If ((QUFN == Zero)) + { + Return ("QCOM0497") + } + Else + { + Return ("QCOM0498") + } + } + + Alias (URSI, _HID) + Name (_CID, "PNP0CA1") // _CID: Compatible ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x04E00000, // Address Base + 0x00100000, // Address Length + ) + }) + Device (USB0) + { + Name (_ADR, Zero) // _ADR: Address + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "BACK", + PLD_VerticalPosition = "CENTER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "VERTICALRECTANGLE", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0xFFFF, + PLD_HorizontalOffset = 0xFFFF) + + }) + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + One, + 0x09, + Zero, + Zero + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x0000011F, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000001C6, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000000D8, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, ) + { + 0x000000DC, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, ) + { + 0x0000014E, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (DPM0, 1, NotSerialized) + { + DPP0 = Arg0 + } + + Method (CCVL, 0, NotSerialized) + { + Return (CCST) /* \_SB_.CCST */ + } + + Method (HSEN, 0, NotSerialized) + { + Return (HSFL) /* \_SB_.HSFL */ + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Switch (ToBuffer (Arg0)) + { + Case (ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899") /* USB Controller */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x1D // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (0x02) + { + Return (Zero) + Break + } + Case (0x03) + { + Return (Zero) + Break + } + Case (0x04) + { + Return (0x02) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + + Method (PHYC, 0, NotSerialized) + { + Name (CFG0, Package (0x00) {}) + Return (CFG0) /* \_SB_.URS0.USB0.PHYC.CFG0 */ + } + } + + Device (UFN0) + { + Name (_ADR, One) // _ADR: Address + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "BACK", + PLD_VerticalPosition = "CENTER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "VERTICALRECTANGLE", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0xFFFF, + PLD_HorizontalOffset = 0xFFFF) + + }) + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + One, + 0x09, + Zero, + Zero + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x0000011F, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000001C6, + } + }) + Method (CCVL, 0, NotSerialized) + { + Return (CCST) /* \_SB_.CCST */ + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Switch (ToBuffer (Arg0)) + { + Case (ToUUID ("fe56cfeb-49d5-4378-a8a2-2978dbe54ad2") /* Unknown UUID */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (One) + { + Return (0x20) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Case (ToUUID ("18de299f-9476-4fc9-b43b-8aeb713ed751") /* Unknown UUID */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (One) + { + Return (0x39) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + + Method (PHYC, 0, NotSerialized) + { + Name (CFG0, Package (0x00) {}) + Return (CFG0) /* \_SB_.URS0.UFN0.PHYC.CFG0 */ + } + } + } diff --git a/Platform/Xiaomi/sm6225/FdtBlob_compat/fog.dtb b/Platform/Xiaomi/sm6225/FdtBlob_compat/fog.dtb new file mode 100755 index 000000000..69e9babf2 Binary files /dev/null and b/Platform/Xiaomi/sm6225/FdtBlob_compat/fog.dtb differ diff --git a/Platform/Xiaomi/sm6225/FdtBlob_compat/spes.dtb b/Platform/Xiaomi/sm6225/FdtBlob_compat/spes.dtb new file mode 100644 index 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a/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_nt36525_hd_plus_vid.xml b/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_nt36525_hd_plus_vid.xml new file mode 100644 index 000000000..6b4d35deb Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_nt36525_hd_plus_vid.xml differ diff --git a/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_cmd.xml b/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_cmd.xml new file mode 100644 index 000000000..340d1438d Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_cmd.xml differ diff --git a/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_vid.xml b/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_vid.xml new file mode 100644 index 000000000..0f8d53b74 Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/Panel_truly_td4330_fhd_vid.xml differ diff --git a/Platform/Xiaomi/sm6225/RawFiles/fog/QcomChargerCfg.cfg b/Platform/Xiaomi/sm6225/RawFiles/fog/QcomChargerCfg.cfg new file mode 100644 index 000000000..06ddd70a6 Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/QcomChargerCfg.cfg differ diff --git a/Platform/Xiaomi/sm6225/RawFiles/fog/SecParti.cfg b/Platform/Xiaomi/sm6225/RawFiles/fog/SecParti.cfg new file mode 100644 index 000000000..475bc0430 Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/SecParti.cfg differ diff --git a/Platform/Xiaomi/sm6225/RawFiles/fog/uefipil.cfg b/Platform/Xiaomi/sm6225/RawFiles/fog/uefipil.cfg new file mode 100644 index 000000000..32629e7ba Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/uefipil.cfg differ diff --git a/Platform/Xiaomi/sm6225/RawFiles/fog/uefiplat.cfg b/Platform/Xiaomi/sm6225/RawFiles/fog/uefiplat.cfg new file mode 100644 index 000000000..e8b71eae5 Binary files /dev/null and b/Platform/Xiaomi/sm6225/RawFiles/fog/uefiplat.cfg differ diff --git a/Platform/Xiaomi/sm6225/fog.dsc b/Platform/Xiaomi/sm6225/fog.dsc new file mode 100644 index 000000000..37c793ded --- /dev/null +++ b/Platform/Xiaomi/sm6225/fog.dsc @@ -0,0 +1,42 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = fog + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm6225/sm6225.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm6225/fog.fdf.inc + + # Enable A/B Slot Environment + AB_SLOTS_SUPPORT = TRUE + +!include Platform/Qualcomm/sm6225/sm6225.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|720 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|1650 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|268 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Redmi 10C" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"fog" + +# Produce the highest video mode in Shell and UiApp +[PcdsDynamicDefault.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 # /8 = column + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 #/19 = row + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 diff --git a/Platform/Xiaomi/sm6225/fog.fdf.inc b/Platform/Xiaomi/sm6225/fog.fdf.inc new file mode 100644 index 000000000..058940a99 --- /dev/null +++ b/Platform/Xiaomi/sm6225/fog.fdf.inc @@ -0,0 +1,17 @@ +// per-device BSP DXEs +INF Platform/EFI_Binaries/Drivers/sm6225/ButtonsDxe/ButtonsDxe.inf + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Platform/Xiaomi/sm6225/AcpiTables/fog/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml + SECTION RAW = Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml + SECTION RAW = Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/Xiaomi/sm6225/FdtBlob_compat/fog.dtb +} + diff --git a/Platform/Xiaomi/sm6225/spes.dsc b/Platform/Xiaomi/sm6225/spes.dsc new file mode 100644 index 000000000..9480d9aea --- /dev/null +++ b/Platform/Xiaomi/sm6225/spes.dsc @@ -0,0 +1,42 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = spes + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm6225/sm6225.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm6225/spes.fdf.inc + + # Enable A/B Slot Environment + AB_SLOTS_SUPPORT = TRUE + +!include Platform/Qualcomm/sm6225/sm6225.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2400 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|409 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Redmi Note 11" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"spes" + +# Produce the highest video mode in Shell and UiApp +[PcdsDynamicDefault.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 # /8 = column + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 #/19 = row + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 \ No newline at end of file diff --git a/Platform/Xiaomi/sm6225/spes.fdf.inc b/Platform/Xiaomi/sm6225/spes.fdf.inc new file mode 100644 index 000000000..e83f66fcc --- /dev/null +++ b/Platform/Xiaomi/sm6225/spes.fdf.inc @@ -0,0 +1,8 @@ +// per-device BSP DXEs + +// ACPI Tables + +FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/Xiaomi/sm6225/FdtBlob_compat/spes.dtb +} + diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.aml b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.aml new file mode 100644 index 000000000..55d210163 Binary files /dev/null and b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.aml differ diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.dsl new file mode 100644 index 000000000..35857ed9d --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.dsl @@ -0,0 +1,99 @@ +DefinitionBlock ("", "DSDT", 2, "QCOMM ", "SM6225 ", 0x00000003) +{ + Scope (_SB) + { + Name (PSUB, "MTP06225") + Name (SOID, 0xFFFFFFFF) + Name (STOR, 0xABCABCAB) + Name (SIDS, "899800000000000") + Name (SIDV, 0xFFFFFFFF) + Name (SVMJ, 0xFFFF) + Name (SVMI, 0xFFFF) + Name (SDFE, 0xFFFF) + Name (SFES, "899800000000000") + Name (SIDM, 0x0000000FFFFFFFFF) + Name (SUFS, 0xFFFFFFFF) + Name (PUS3, 0xFFFFFFFF) + Name (SUS3, 0xFFFFFFFF) + Name (SIDT, 0xFFFFFFFF) + Name (SOSN, 0xAAAAAAAABBBBBBBB) + Name (PLST, 0xFFFFFFFF) + Name (EMUL, 0xFFFFFFFF) + Name (SJTG, 0xFFFFFFFF) + Name (RMTB, 0xAAAAAAAA) + Name (RMTX, 0xBBBBBBBB) + Name (RFMB, 0xCCCCCCCC) + Name (RFMS, 0xDDDDDDDD) + Name (RFAB, 0xEEEEEEEE) + Name (RFAS, 0x77777777) + Name (TCMA, 0xDEADBEEF) + Name (TCML, 0xBEEFDEAD) + Name (SOSI, 0xDEADBEEFFFFFFFFF) + Name (PRP0, 0xFFFFFFFF) + Name (PRP1, 0xFFFFFFFF) + Name (PRP2, 0xFFFFFFFF) + Name (PRP3, 0xFFFFFFFF) + Name (PRP4, 0xFFFFFFFF) + Name (PRP5, 0xFFFFFFFF) + Name (PRP6, 0xFFFFFFFF) + + Device (UFS0) + { + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_HID, "QCOM24A5") // _HID: Hardware ID + Alias (^EMUL, EMUL) + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x04804000, // Address Base + 0x00014000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000184, + } + }) + Return (RBUF) /* \_SB_.UFS0._CRS.RBUF */ + } + + Device (DEV0) + { + Method (_ADR, 0, NotSerialized) // _ADR: Address + { + Return (0x08) + } + + Method (_RMV, 0, NotSerialized) // _RMV: Removal Status + { + Return (Zero) + } + } + } + + Include("abd.dsl") + + Include("pmic_core.dsl") + + Include("scm.dsl"); + + Include("spmi.dsl"); + + Include("qcgpio.dsl"); + + Include("btns.dsl"); + + Include("pep_lpi.dsl"); + + Include("usb.dsl"); + + } +} + diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/abd.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/abd.dsl new file mode 100644 index 000000000..e8762357b --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/abd.dsl @@ -0,0 +1,20 @@ +Device (ABD) +{ + Name (_HID, "QCOM0527") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (ROP1, GenericSerialBus, Zero, 0x0100) + Name (AVBL, Zero) + Alias (PSUB, _SUB) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If ((Arg0 == 0x09)) + { + AVBL = Arg1 + } + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0xF) + } +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/btns.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/btns.dsl new file mode 100644 index 000000000..6f1295bbe --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/btns.dsl @@ -0,0 +1,74 @@ +Device (BTNS) +{ + Name (_HID, "ACPI0011" /* Generic Buttons Device */) // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveBoth, ExclusiveAndWake, PullDown, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0000 + } + GpioInt (Edge, ActiveBoth, Exclusive, PullUp, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0085 + } + GpioInt (Edge, ActiveBoth, Exclusive, PullDown, 0x0000, + "\\_SB.PM01", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x0001 + } + }) + Return (RBUF) /* \_SB_.BTNS._CRS.RBUF */ + } + + Name (_DSD, Package (0x02) // _DSD: Device-Specific Data + { + ToUUID ("fa6bd625-9ce8-470d-a2c7-b3ca36c4282e") /* Generic Buttons Device */, + Package (0x04) + { + Package (0x05) // Portable Device Control + { + Zero, + One, + Zero, + One, + 0x0D + }, + + Package (0x05) // Power + { + One, + Zero, + One, + One, + 0x81 + }, + + Package (0x05) // Vol Up + { + One, + One, + One, + 0x0C, + 0xE9 + }, + + Package (0x05) // Vol Down + { + One, + 0x02, + One, + 0x0C, + 0xEA + } + } + }) +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/gpio.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/gpio.dsl new file mode 100644 index 000000000..533a449b3 --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/gpio.dsl @@ -0,0 +1,90 @@ + Device (GIO0) + { + Name (_HID, "QCOM050D") // _HID: Hardware ID + Name (_CID, "QCOMFFE3") // _CID: Compatible ID + Name (_UID, Zero) // _UID: Unique ID + Alias (\_SB.PSUB, _SUB) + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x00400000, // Address Base + 0x00C00000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000103, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000249, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Shared, ,, ) + { + 0x0000025B, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000259, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x0000022C, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x0000024E, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000292, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000239, + } + }) + Return (RBUF) /* \_SB_.GIO0._CRS.RBUF */ + } + + Method (OFNI, 0, NotSerialized) + { + Name (RBUF, Buffer (0x02) + { + 0xAF, 0x00 // .. + }) + Return (RBUF) /* \_SB_.GIO0.OFNI.RBUF */ + } + + Name (GABL, Zero) + Method (_REG, 2, NotSerialized) // _REG: Region Availability + { + If ((Arg0 == 0x08)) + { + GABL = Arg1 + } + } + + Name (_AEI, ResourceTemplate () // _AEI: ACPI Event Interrupts + { + GpioInt (Edge, ActiveHigh, Exclusive, PullDown, 0x01F4, + "\\_SB.GIO0", 0x00, ResourceConsumer, , + ) + { // Pin list + 0x00BD + } + }) + Method (_EBD, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.GPU0, 0x92) // Device-Specific + } + } \ No newline at end of file diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/pep_lpi.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/pep_lpi.dsl new file mode 100644 index 000000000..8884bbe03 --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/pep_lpi.dsl @@ -0,0 +1,1680 @@ + Device (SYSM) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x00100000) // _UID: Unique ID + Device (APC0) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x0100) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x02000000, + 0x03, + Package (0x0A) + { + 0x0BB8, + 0x044C, + One, + Zero, + Zero, + Zero, + 0x0400, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "CCI.E3" + }, + + Package (0x0A) + { + 0x0DAC, + 0x047E, + One, + Zero, + Zero, + Zero, + 0x0500, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "CCI.E3+RPM" + }, + + Package (0x0A) + { + 0x80E8, + 0x01F4, + One, + 0x20, + Zero, + Zero, + 0x0300, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "platform.xo" + } + }) + Device (CL0) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x01000000, + 0x03, + Package (0x0A) + { + 0x012C, + 0x82, + Zero, + Zero, + Zero, + Zero, + 0x20, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D2d" + }, + + Package (0x0A) + { + 0x015E, + 0x96, + Zero, + Zero, + Zero, + Zero, + 0x30, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D2e" + }, + + Package (0x0A) + { + 0x1900, + 0x0384, + One, + Zero, + Zero, + 0x03, + 0x40, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Silver.D4" + } + }) + Device (CPU0) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver0.C3_NI" + } + }) + } + + Device (CPU1) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver1.C3_NI" + } + }) + } + + Device (CPU2) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver2.C3_NI" + } + }) + } + + Device (CPU3) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C1" + }, + + Package (0x0A) + { + 0x0190, + 0x64, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C2d" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C3" + }, + + Package (0x0A) + { + 0x01C2, + 0x012C, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoSilver3.C3_NI" + } + }) + } + } + + Device (CL1) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_UID, 0x20) // _UID: Unique ID + Name (_LPI, Package (0x06) // _LPI: Low Power Idle States + { + Zero, + 0x01000000, + 0x03, + Package (0x0A) + { + 0x0384, + 0xC8, + Zero, + Zero, + Zero, + Zero, + 0x20, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D2d" + }, + + Package (0x0A) + { + 0x03E8, + 0x0190, + Zero, + Zero, + Zero, + Zero, + 0x30, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D2e" + }, + + Package (0x0A) + { + 0x1770, + 0x04B0, + One, + Zero, + Zero, + 0x03, + 0x40, + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "L2_Gold.D4" + } + }) + Device (CPU4) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold0.C3_NI" + } + }) + } + + Device (CPU5) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold1.C3_NI" + } + }) + } + + Device (CPU6) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold2.C3_NI" + } + }) + } + + Device (CPU7) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (_LPI, Package (0x07) // _LPI: Low Power Idle States + { + Zero, + Zero, + 0x04, + Package (0x0A) + { + Zero, + Zero, + One, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x00000000FFFFFFFF, // Address + 0x04, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C1" + }, + + Package (0x0A) + { + 0x0258, + 0x50, + Zero, + Zero, + Zero, + Zero, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000000000002, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C2d" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + One, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000003, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C3" + }, + + Package (0x0A) + { + 0x1B58, + 0x5A, + Zero, + One, + Zero, + 0x03, + ResourceTemplate () + { + Register (FFixedHW, + 0x20, // Bit Width + 0x00, // Bit Offset + 0x0000000040000004, // Address + 0x03, // Access Size + ) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + ResourceTemplate () + { + Register (SystemMemory, + 0x00, // Bit Width + 0x00, // Bit Offset + 0x0000000000000000, // Address + ,) + }, + + "KryoGold3.C3_NI" + } + }) + } + } + } + } diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/pmic_core.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/pmic_core.dsl new file mode 100644 index 000000000..89a2efbb5 --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/pmic_core.dsl @@ -0,0 +1,200 @@ +Device (PMIC) +{ + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + SPMI + }) + Name (_HID, "QCOM052E") // _HID: Hardware ID + Name (_CID, "PNP0CA3") // _CID: Compatible ID + Alias (PSUB, _SUB) + Method (PMCF, 0, NotSerialized) + { + Name (CFG0, Package (0x04) + { + 0x02, + Package (0x02) + { + Zero, + One + }, + + Package (0x02) + { + 0x02, + 0x03 + } + }) + Return (CFG0) /* \_SB_.PMIC.PMCF.CFG0 */ + } +} + +Device (PM01) +{ + Name (_HID, "QCOM0530") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, One) // _UID: Unique ID + Name (_DEP, Package (One) // _DEP: Dependencies + { + PMIC + }) + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x000000D7, + } + }) + Return (RBUF) /* \_SB_.PM01._CRS.RBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + While (One) + { + Name (_T_0, Buffer (0x01) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z + { + 0x00 // . + }) + CopyObject (ToBuffer (Arg0), _T_0) /* \_SB_.PM01._DSM._T_0 */ + If ((_T_0 == ToUUID ("4f248f40-d5e2-499f-834c-27758ea1cd3f") /* GPIO Controller */)) + { + While (One) + { + Name (_T_1, 0x00) // _T_x: Emitted by ASL Compiler, x=0-9, A-Z + _T_1 = ToInteger (Arg2) + If ((_T_1 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + ElseIf ((_T_1 == One)) + { + Return (Package (0x02) + { + Zero, + One + }) + } + Else + { + } + + Break + } + } + Else + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Break + } + } +} + +Device (PMAP) +{ + Name (_HID, "QCOM052F") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_DEP, Package (0x03) // _DEP: Dependencies + { + PMIC, + ABD, + SCM0 + }) + Method (GEPT, 0, NotSerialized) + { + Name (BUFF, Buffer (0x04){}) + CreateByteField (BUFF, Zero, STAT) + CreateWordField (BUFF, 0x02, DATA) + DATA = 0x02 + Return (DATA) /* \_SB_.PMAP.GEPT.DATA */ + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, Buffer (0x02) + { + 0x79, 0x00 // y. + }) + Return (RBUF) /* \_SB_.PMAP._CRS.RBUF */ + } +} + +Device (PRTC) +{ + Name (_HID, "ACPI000E" /* Time and Alarm Device */) // _HID: Hardware ID + Name (_DEP, Package (0x01) // _DEP: Dependencies + { + PMAP + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (_GCP, 0, NotSerialized) // _GCP: Get Capabilities + { + Return (0x04) + } + + Field (\_SB.ABD.ROP1, BufferAcc, NoLock, Preserve) + { + Connection ( + I2cSerialBusV2 (0x0002, ControllerInitiated, 0x00000000, + AddressingMode7Bit, "\\_SB.ABD", + 0x00, ResourceConsumer, , Exclusive, + ) + ), + AccessAs (BufferAcc, AttribRawBytes (0x18)), + FLD0, 192 + } + + Method (_GRT, 0, NotSerialized) // _GRT: Get Real Time + { + Name (BUFF, Buffer (0x1A){}) + CreateField (BUFF, 0x10, 0x80, TME1) + CreateField (BUFF, 0x90, 0x20, ACT1) + CreateField (BUFF, 0xB0, 0x20, ACW1) + BUFF = FLD0 /* \_SB_.PRTC.FLD0 */ + Return (TME1) /* \_SB_.PRTC._GRT.TME1 */ + } + + Method (_SRT, 1, NotSerialized) // _SRT: Set Real Time + { + Name (BUFF, Buffer (0x32){}) + CreateByteField (BUFF, Zero, STAT) + CreateField (BUFF, 0x10, 0x80, TME1) + CreateField (BUFF, 0x90, 0x20, ACT1) + CreateField (BUFF, 0xB0, 0x20, ACW1) + ACT1 = Zero + TME1 = Arg0 + ACW1 = Zero + BUFF = FLD0 = BUFF /* \_SB_.PRTC._SRT.BUFF */ + If ((STAT != Zero)) + { + Return (One) + } + + Return (Zero) + } +} + +Device (PEXT) +{ + Name (_DEP, Package (0x02) // _DEP: Dependencies + { + SPMI, + PMIC + }) + Name (_HID, "QCOM05CE") // _HID: Hardware ID + Alias (PSUB, _SUB) +} diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/qcgpio.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/qcgpio.dsl new file mode 100644 index 000000000..44067b4d9 --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/qcgpio.dsl @@ -0,0 +1,41 @@ +Device (GIO0) +{ + Name (_HID, "QCOM0217") + Alias(\_SB.PSUB, _SUB) + Name (_UID, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // TLMM register address space + Memory32Fixed (ReadWrite, 0x00400000, 0x00C00000) + + // Summary Interrupt shared by all banks + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Level, ActiveHigh, Shared, , , ) {240} + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {648} // For PDC Wake up ::TLMM GPIo 126 SD Card Detection + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {568} // For PDC Wake up ::TLMM GPIo 54 + Interrupt(ResourceConsumer, Edge, ActiveBoth, Shared, , , ) {646} // For PDC Wake up ::TLMM GPIo 124, Hall sensor used for lid + }) + Return (RBUF) + } + // ACPI method to return Num pins + Method(OFNI, 0x0, NotSerialized) { + Name(RBUF, Buffer() + { + 0x96, // 0: TOTAL_GPIO_PINS + 0x00 // 1: TOTAL_GPIO_PINS + }) + Return (RBUF) + } + + Name(GABL, Zero) + Method(_REG, 0x2, NotSerialized) + { + If(LEqual(Arg0, 0x8)) + { + Store(Arg1, GABL) + } + } +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/scm.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/scm.dsl new file mode 100644 index 000000000..3c6567239 --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/scm.dsl @@ -0,0 +1,6 @@ +Device (SCM0) +{ + Name (_HID, "QCOM050B") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID +} \ No newline at end of file diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/spmi.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/spmi.dsl new file mode 100644 index 000000000..3550574f0 --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/spmi.dsl @@ -0,0 +1,31 @@ +Device (SPMI) +{ + Name (_HID, "QCOM050C") // _HID: Hardware ID + Alias (PSUB, _SUB) + Name (_CID, "PNP0CA2") // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, + 0x01C00000, // Address Base + 0x02800000, // Address Length + ) + }) + Return (RBUF) /* \_SB_.SPMI._CRS.RBUF */ + } + + Method (CONF, 0, NotSerialized) + { + Name (XBUF, Buffer (0x1A) + { + /* 0000 */ 0x00, 0x01, 0x01, 0x01, 0xFF, 0x00, 0x02, 0x00, // ........ + /* 0008 */ 0x0A, 0x07, 0x04, 0x07, 0x01, 0xFF, 0x10, 0x01, // ........ + /* 0010 */ 0x00, 0x01, 0x01, 0xC0, 0x00, 0x00, 0x02, 0x80, // ...@.... + /* 0018 */ 0x00, 0x00 // .. + }) + Return (XBUF) /* \_SB_.SPMI.CONF.XBUF */ + } +} diff --git a/Platform/Xiaomi/sm6375/AcpiTables/moonstone/usb.dsl b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/usb.dsl new file mode 100644 index 000000000..1dbe690fc --- /dev/null +++ b/Platform/Xiaomi/sm6375/AcpiTables/moonstone/usb.dsl @@ -0,0 +1,416 @@ +Name (QUFN, Zero) + Name (DPP0, Buffer (One) + { + 0x00 // . + }) + Name (DPP1, Buffer (One) + { + 0x00 // . + }) + Name (MPP0, Buffer (One) + { + 0x00 // . + }) + Name (MPP1, Buffer (One) + { + 0x00 // . + }) + Name (HPDB, Zero) + Name (HPDS, Buffer (One) + { + 0x00 // . + }) + Name (PINA, Zero) + Name (DPPN, 0x0D) + Name (CCST, Buffer (One) + { + 0x02 // . + }) + Name (PORT, Buffer (One) + { + 0x02 // . + }) + Name (HIRQ, Buffer (One) + { + 0x00 // . + }) + Name (HSFL, Buffer (One) + { + 0x00 // . + }) + Name (USBC, Buffer (One) + { + 0x0B // . + }) + Name (MUXC, Buffer (One) + { + 0x00 // . + }) + Device (URS0) + { + Method (URSI, 0, NotSerialized) + { + If ((QUFN == Zero)) + { + Return ("QCOM0497") + } + Else + { + Return ("QCOM0498") + } + } + + Alias (URSI, _HID) + Name (_CID, "PNP0CA1") // _CID: Compatible ID + Alias (PSUB, _SUB) + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, Zero) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x04E00000, // Address Base + 0x00100000, // Address Length + ) + }) + Device (USB0) + { + Name (_ADR, Zero) // _ADR: Address + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "BACK", + PLD_VerticalPosition = "CENTER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "VERTICALRECTANGLE", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0xFFFF, + PLD_HorizontalOffset = 0xFFFF) + + }) + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + One, + 0x09, + Zero, + Zero + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x0000011F, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000001C6, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000000D8, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, ) + { + 0x000000DC, + } + Interrupt (ResourceConsumer, Edge, ActiveHigh, SharedAndWake, ,, ) + { + 0x0000014E, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (DPM0, 1, NotSerialized) + { + DPP0 = Arg0 + } + + Method (CCVL, 0, NotSerialized) + { + Return (CCST) /* \_SB_.CCST */ + } + + Method (HSEN, 0, NotSerialized) + { + Return (HSFL) /* \_SB_.HSFL */ + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Switch (ToBuffer (Arg0)) + { + Case (ToUUID ("ce2ee385-00e6-48cb-9f05-2edb927c4899") /* USB Controller */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x1D // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (0x02) + { + Return (Zero) + Break + } + Case (0x03) + { + Return (Zero) + Break + } + Case (0x04) + { + Return (0x02) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + + Method (PHYC, 0, NotSerialized) + { + Name (CFG0, Package (0x00) {}) + Return (CFG0) /* \_SB_.URS0.USB0.PHYC.CFG0 */ + } + } + + Device (UFN0) + { + Name (_ADR, One) // _ADR: Address + Name (_S0W, 0x03) // _S0W: S0 Device Wake State + Name (_PLD, Package (0x01) // _PLD: Physical Location of Device + { + ToPLD ( + PLD_Revision = 0x2, + PLD_IgnoreColor = 0x1, + PLD_Red = 0x0, + PLD_Green = 0x0, + PLD_Blue = 0x0, + PLD_Width = 0x0, + PLD_Height = 0x0, + PLD_UserVisible = 0x1, + PLD_Dock = 0x0, + PLD_Lid = 0x0, + PLD_Panel = "BACK", + PLD_VerticalPosition = "CENTER", + PLD_HorizontalPosition = "LEFT", + PLD_Shape = "VERTICALRECTANGLE", + PLD_GroupOrientation = 0x0, + PLD_GroupToken = 0x0, + PLD_GroupPosition = 0x0, + PLD_Bay = 0x0, + PLD_Ejectable = 0x0, + PLD_EjectRequired = 0x0, + PLD_CabinetNumber = 0x0, + PLD_CardCageNumber = 0x0, + PLD_Reference = 0x0, + PLD_Rotation = 0x0, + PLD_Order = 0x0, + PLD_VerticalOffset = 0xFFFF, + PLD_HorizontalOffset = 0xFFFF) + + }) + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + One, + 0x09, + Zero, + Zero + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x0000011F, + } + Interrupt (ResourceConsumer, Level, ActiveHigh, SharedAndWake, ,, ) + { + 0x000001C6, + } + }) + Method (CCVL, 0, NotSerialized) + { + Return (CCST) /* \_SB_.CCST */ + } + + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + Switch (ToBuffer (Arg0)) + { + Case (ToUUID ("fe56cfeb-49d5-4378-a8a2-2978dbe54ad2") /* Unknown UUID */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (One) + { + Return (0x20) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Case (ToUUID ("18de299f-9476-4fc9-b43b-8aeb713ed751") /* Unknown UUID */) { Switch (ToInteger (Arg2)) + { + Case (Zero) + { + Switch (ToInteger (Arg1)) + { + Case (Zero) + { + Return (Buffer (One) + { + 0x03 // . + }) + Break + } + Default + { + Return (Buffer (One) + { + 0x01 // . + }) + Break + } + + } + + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + Case (One) + { + Return (0x39) + Break + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + Default + { + Return (Buffer (One) + { + 0x00 // . + }) + Break + } + + } + } + + Method (PHYC, 0, NotSerialized) + { + Name (CFG0, Package (0x00) {}) + Return (CFG0) /* \_SB_.URS0.UFN0.PHYC.CFG0 */ + } + } + } diff --git a/Platform/Xiaomi/sm6375/FdtBlob_compat/moonstone.dtb b/Platform/Xiaomi/sm6375/FdtBlob_compat/moonstone.dtb new file mode 100644 index 000000000..fad07e379 Binary files /dev/null and b/Platform/Xiaomi/sm6375/FdtBlob_compat/moonstone.dtb differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/BATTERY.PROVISION b/Platform/Xiaomi/sm6375/RawFiles/moonstone/BATTERY.PROVISION new file mode 100644 index 000000000..3274253c1 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/BATTERY.PROVISION differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/BDS_Menu.cfg b/Platform/Xiaomi/sm6375/RawFiles/moonstone/BDS_Menu.cfg new file mode 100644 index 000000000..3f5ce79ac Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/BDS_Menu.cfg differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_35_02_0a_fhdp_video.xml b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_35_02_0a_fhdp_video.xml new file mode 100644 index 000000000..85567b652 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_35_02_0a_fhdp_video.xml differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_43_03_0b_fhdp_video.xml b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_43_03_0b_fhdp_video.xml new file mode 100644 index 000000000..2e71ac152 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_43_03_0b_fhdp_video.xml differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_c3q_45_02_0c_fhdp_video.xml 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b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_truly_td4330_fhd_cmd.xml new file mode 100644 index 000000000..340d1438d Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_truly_td4330_fhd_cmd.xml differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_truly_td4330_fhd_vid.xml b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_truly_td4330_fhd_vid.xml new file mode 100644 index 000000000..0f8d53b74 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/Panel_truly_td4330_fhd_vid.xml differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/QcomChargerCfg.cfg b/Platform/Xiaomi/sm6375/RawFiles/moonstone/QcomChargerCfg.cfg new file mode 100644 index 000000000..06ddd70a6 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/QcomChargerCfg.cfg differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/SecParti.cfg b/Platform/Xiaomi/sm6375/RawFiles/moonstone/SecParti.cfg new file mode 100644 index 000000000..475bc0430 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/SecParti.cfg differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/uefipil.cfg b/Platform/Xiaomi/sm6375/RawFiles/moonstone/uefipil.cfg new file mode 100644 index 000000000..32629e7ba Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/uefipil.cfg differ diff --git a/Platform/Xiaomi/sm6375/RawFiles/moonstone/uefiplat.cfg b/Platform/Xiaomi/sm6375/RawFiles/moonstone/uefiplat.cfg new file mode 100644 index 000000000..e8b71eae5 Binary files /dev/null and b/Platform/Xiaomi/sm6375/RawFiles/moonstone/uefiplat.cfg differ diff --git a/Platform/Xiaomi/sm6375/moonstone.dsc b/Platform/Xiaomi/sm6375/moonstone.dsc new file mode 100644 index 000000000..ffda0712c --- /dev/null +++ b/Platform/Xiaomi/sm6375/moonstone.dsc @@ -0,0 +1,42 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = moonstone + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm6375/sm6375.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm6375/moonstone.fdf.inc + + # Enable A/B Slot Environment + AB_SLOTS_SUPPORT = TRUE + +!include Platform/Qualcomm/sm6375/sm6375.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|720 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|1650 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|268 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"POCO X5 5G" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"moonstone" + +# Produce the highest video mode in Shell and UiApp +[PcdsDynamicDefault.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 # /8 = column + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 #/19 = row + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0 diff --git a/Platform/Xiaomi/sm6375/moonstone.fdf.inc b/Platform/Xiaomi/sm6375/moonstone.fdf.inc new file mode 100644 index 000000000..c2095fe48 --- /dev/null +++ b/Platform/Xiaomi/sm6375/moonstone.fdf.inc @@ -0,0 +1,17 @@ +// per-device BSP DXEs +INF Platform/EFI_Binaries/Drivers/sm6225/ButtonsDxe/ButtonsDxe.inf + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Platform/Xiaomi/sm6375/AcpiTables/moonstone/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sm6375/AcpiTables/MADT.aml + SECTION RAW = Silicon/Qualcomm/sm6375/AcpiTables/FADT.aml + SECTION RAW = Silicon/Qualcomm/sm6375/AcpiTables/GTDT.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob + FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/Xiaomi/sm6375/FdtBlob_compat/moonstone.dtb +} + diff --git a/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml b/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_HUAXING.aml similarity index 71% rename from Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml rename to Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_HUAXING.aml index 6e73bd0f4..3ce1bf531 100644 Binary files a/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml and b/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_HUAXING.aml differ diff --git a/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_TIANMA.aml b/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_TIANMA.aml new file mode 100644 index 000000000..ace096f86 Binary files /dev/null and b/Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_TIANMA.aml differ diff --git a/Platform/Xiaomi/sm7125/miatoll-huaxing.sh.inc b/Platform/Xiaomi/sm7125/miatoll-huaxing.sh.inc new file mode 100644 index 000000000..0a99d85be --- /dev/null +++ b/Platform/Xiaomi/sm7125/miatoll-huaxing.sh.inc @@ -0,0 +1,5 @@ +function platform_pre_acpi(){ + cp Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_HUAXING.aml Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml + DEVICE="miatoll" + EXT="-huaxing" +} diff --git a/Platform/Xiaomi/sm7125/miatoll-tianma.sh.inc b/Platform/Xiaomi/sm7125/miatoll-tianma.sh.inc new file mode 100644 index 000000000..53ba8b732 --- /dev/null +++ b/Platform/Xiaomi/sm7125/miatoll-tianma.sh.inc @@ -0,0 +1,5 @@ +function platform_pre_acpi(){ + cp Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT_TIANMA.aml Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml + DEVICE="miatoll" + EXT="-tianma" +} diff --git a/Platform/Xiaomi/sm7125/miatoll.fdf.inc b/Platform/Xiaomi/sm7125/miatoll.fdf.inc index de601d33e..38e57800b 100644 --- a/Platform/Xiaomi/sm7125/miatoll.fdf.inc +++ b/Platform/Xiaomi/sm7125/miatoll.fdf.inc @@ -1,16 +1,23 @@ + + // ACPI Tables FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { # Customized DSDT SECTION RAW = Platform/Xiaomi/sm7125/AcpiTables/miatoll/DSDT.aml # Common Tables -# SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/DBG2.aml - SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACP.aml - SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/GTDT.aml -# SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/IORT.aml - SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MADT.aml - SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/PPTT.aml - SECTION UI = "AcpiTables" + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/APIC.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/CSRT.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/DBG2.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACP.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACS.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/GTDT.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/IORT.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MCFG.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/PPTT.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/SPCR.aml + SECTION RAW = Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/TPM2.aml + SECTION UI = "AcpiTables" } diff --git a/Platform/Xiaomi/sm7325/lisa.dsc b/Platform/Xiaomi/sm7325/lisa.dsc index 2f3880881..22bac8893 100644 --- a/Platform/Xiaomi/sm7325/lisa.dsc +++ b/Platform/Xiaomi/sm7325/lisa.dsc @@ -24,5 +24,5 @@ gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|440 gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" - gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Lite NE 5G" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Mi 11 Lite NE" gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"lisa" diff --git a/Platform/Xiaomi/sm8150/AcpiTables/cepheus/DSDT.aml b/Platform/Xiaomi/sm8150/AcpiTables/cepheus/DSDT.aml index 2496731d5..10347ff55 100644 Binary files a/Platform/Xiaomi/sm8150/AcpiTables/cepheus/DSDT.aml and b/Platform/Xiaomi/sm8150/AcpiTables/cepheus/DSDT.aml differ diff --git a/Platform/Xiaomi/sm8150/AcpiTables/nabu/DSDT.aml b/Platform/Xiaomi/sm8150/AcpiTables/nabu/DSDT.aml index ca55e4c57..fb90386a0 100644 Binary files a/Platform/Xiaomi/sm8150/AcpiTables/nabu/DSDT.aml and b/Platform/Xiaomi/sm8150/AcpiTables/nabu/DSDT.aml differ diff --git a/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_HUAXING.aml b/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_HUAXING.aml index b836abd36..661809ff7 100755 Binary files a/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_HUAXING.aml and b/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_HUAXING.aml differ diff --git a/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_TIANMA.aml b/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_TIANMA.aml index eeba62141..e47f7df47 100755 Binary files a/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_TIANMA.aml and b/Platform/Xiaomi/sm8150/AcpiTables/vayu/DSDT_TIANMA.aml differ diff --git a/Platform/Xiaomi/sm8250/AcpiTables/alioth/DSDT.aml b/Platform/Xiaomi/sm8250/AcpiTables/alioth/DSDT.aml index f1dd24e6b..9fe87e834 100644 Binary files a/Platform/Xiaomi/sm8250/AcpiTables/alioth/DSDT.aml and b/Platform/Xiaomi/sm8250/AcpiTables/alioth/DSDT.aml differ diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/DSDT.aml b/Platform/Xiaomi/sm8250/AcpiTables/lmi/DSDT.aml new file mode 100644 index 000000000..9fe87e834 Binary files /dev/null and b/Platform/Xiaomi/sm8250/AcpiTables/lmi/DSDT.aml differ diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/Dsdt.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Dsdt.asl new file mode 100644 index 000000000..dbe7b2285 --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Dsdt.asl @@ -0,0 +1,24 @@ +// +// NOTE: The 3rd parameter (i.e. ComplianceRevision) must be >=2 for 64-bit integer support. +// +DefinitionBlock("DSDT.AML", "DSDT", 0x02, "QCOMM ", "SDM850 ", 3) +{ + Scope(\_SB_) { + + // Include("addSub.asl") + Include("dsdt_common.asl") + // Include("cust_dsdt.asl") + + // Include("usb.asl") + + // + // Buttons + // + // Include("cust_arraybutton.asl") + + // + // Bluetooth + // + // Include("wcnss_bt.asl") + } +} diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/Pep_lpi.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Pep_lpi.asl new file mode 100644 index 000000000..08364a758 --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/Pep_lpi.asl @@ -0,0 +1,646 @@ +Device (SYSM) { + Name (_HID, "ACPI0010") + Name (_UID, 0x100000) + Name (_LPI, Package() + { + 0, // Version + 0x1000000, // Level ID + 1, // Count + + // DRIPS State - Xo Shutdown + Cx retention + AOSS Sleep + LLC deactivate + Package () { + 9500, // Min residency (us) + 6000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0x20, // Arch context last flags + 0x20 For Debugger Transistion by PEP. + 0, // Residency counter frequency + 0, // Enabled parent state + 0xB300, // Integer entry method PSCI E3 + F3 + LLC + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "platform.DRIPS" // Name + } + }) // End of _LPI + + + Device (CLUS) + { + Name (_HID, "ACPI0010") + Name (_UID, 0x10) + Name (_LPI, Package() + { + 0, // Version + 0x1000000, // Level ID + 2, // Count + + // State 0: D2 + Package () + { + 5900, // Min residency (us) + 3000, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + 0x20, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D2" // Name + }, + // State 1: D4 + Package () + { + 6000, // Min residency (us) + 3300, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Till F1) + 0x40, // Integer entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "L3Cluster.D4" // Name + } + }) // End of _LPI + + + Device (CPU0) // Kryo Silver CPU0 < SYSM.CLUS.CPU0 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x0) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver0.C4" // Name + } + + }) // End of _LPI + } // End of CPU0 + + Device (CPU1) // Kyro Silver CPU1 < SYSM.CLUS.CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x1) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver1.C4" // Name + } + + }) // End of _LPI + } // End of CPU1 + + Device (CPU2) // Kyro Silver CPU2 < SYSM.CLUS.CPU1 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x2) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver2.C4" // Name + } + + }) // End of _LPI + } // End of CPU2 + + Device (CPU3) // Kyro Silver CPU3 < SYSM.CLUS.CPU3 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x3) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C2" // Name + }, + // C3 + Package () + { + 1774, // Min residency (us) + 901, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C3" // Name + }, + // C4 + Package () + { + 4001, // Min residency (us) + 915, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoSilver3.C4" // Name + } + + }) // End of _LPI + } // End of CPU3 + + Device (CPU4) // Kryo Gold CPU0 < SYSM.CLUS.CPU4 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x4) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables LLC) + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold0.C4" // Name + } + }) // End of _LPI + } // End of CPU4 + + Device (CPU5) // Kryo Gold CPU1 < SYSM.CLUS.CPU5 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x5) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold1.C4" // Name + } + }) // End of _LPI + } // End of CPU5 + + Device (CPU6) // Kryo Gold CPU2 < SYSM.CLUS.CPU6 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x6) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C2" // Name + }, + // C3 + Package () + { + 3850, // Min residency (us) + 860, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C3" // Name + }, + // C4 + Package () + { + 3950, // Min residency (us) + 910, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoGold2.C4" // Name + } + }) // End of _LPI + } // End of CPU6 + + Device (CPU7) // Kryo Prime CPU0 < SYSM.CLUS.CPU7 + { + Name (_HID, "ACPI0007") + Name (_UID, 0x7) + Method(_STA){ Return (0xF) } + + Name (_LPI, Package() + { + 0, // Version + 0, // Level ID + 4, // Count + + // Core Clock Gate - C1 + Package () + { + 0, // Min residency (us) + 0, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 0, // Enabled parent state + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x00000000FFFFFFFF, 3)}, // Register entry method <= WFI + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C1" // Name + }, + // C2 + Package () + { + 400, // Min residency (us) + 100, // Wake latency (us) + 0, // Flags, set bit0 to 1 to enable this state + 0, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state + // Register (AddressSpaceKeyword, RegisterBitWidth, RegisterBitOffset, RegisterAddress, AccessSize, DescriptorName) + ResourceTemplate(){Register(FFixedHW, 0x20, 0, 0x0000000000000002, 3)}, // Register entry method + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C2" // Name + }, + // C3 + Package () + { + 3990, // Min residency (us) + 1000, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 1, // Enabled parent state (Enables D4) 0x40000003 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000003,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C3" // Name + }, + // C4 + Package () + { + 4490, // Min residency (us) + 1500, // Wake latency (us) + 1, // Flags, set bit0 to 1 to enable this state + 1, // Arch context last flags + 0, // Residency counter frequency + 2, // Enabled parent state (Enables D4) 0x40000004 + ResourceTemplate(){Register(FFixedHW, 0x20, 0,0x0000000040000004,3)}, // Core collapse. + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Residency counter register + ResourceTemplate(){Register(SystemMemory,0,0,0,0)}, // Usage counter register + "KryoPrime0.C4" // Name + } + }) // End of _LPI + } // End of CPU7 + } // End of CLUS +} // End of SYSM diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/dsdt_common.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/dsdt_common.asl new file mode 100644 index 000000000..b60b66782 --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/dsdt_common.asl @@ -0,0 +1,103 @@ +Name(SOID, 0xffffffff) // Holds the Chip Id +Name(STOR, 0x1) // Holds boot options 0 = nvme, 1 = ufs +Name(SIDS, "899800000000000") // Holds the Chip ID translated to a string +Name(SIDV, 0xffffffff) // Holds the Chip Version as (major<<16)|(minor&0xffff) +Name(SVMJ, 0xffff) // Holds the major Chip Version +Name(SVMI, 0xffff) // Holds the minor Chip Version +Name(SDFE, 0xffff) // Holds the Chip Family enum +Name(SFES, "899800000000000") // Holds the Chip Family translated to a string +Name(SIDM, 0xfffffffff) // Holds the Modem Support bit field +Name(SUFS, 0x0) // Holds secondary UFS enablement (1 = enabled) +Name(PUS3, 0x0) // Holds whether primary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SUS3, 0x0) // Holds whether secondary UFS has 3.0 part (1 = UFS 3.0 and newer) +Name(SIDT, 0xffffffff) // Holds the Chip Tier value +Name(SJTG, 0xffffffff) // Holds the JTAG ID +Name(SOSN, 0xaaaaaaaabbbbbbbb) // Holds the Chip Serial Number +Name(PLST, 0xffffffff) // Holds the Device platform subtype +Name(EMUL, 0xffffffff) // Holds the Device emulation type +Name (RMTB, 0xaaaaaaaa) // Holds the RemoteFS shared memory base address +Name (RMTX, 0xbbbbbbbb) // Holds the RemoteFS shared memory length +Name (RFMB, 0xcccccccc) // Holds the RFSA MPSS shared memory base address +Name (RFMS, 0xdddddddd) // Holds the RFSA MPSS shared memory length +Name (RFAB, 0xeeeeeeee) // Holds the RFSA ADSP shared memory base address +Name (RFAS, 0x77777777) // Holds the RFSA ADSP shared memory length +Name (TCMA, 0xDEADBEEF) // Holds TrEE Carveout Memory Address +Name (TCML, 0xBEEFDEAD) // Holds TrEE Carveout Memory Length +Name (SOSI, 0xdeadbeefffffffff) // Holds the base address of the SoCInfo shared memory region used by ChipInfoLib +Name (PRP1, 0xFFFFFFFF) // 0xFFFFFFFF - PCIe state unknown : 0x00000001 - PCIe root port 1 present : 0x00000000 - PCIe root port 1 not present +Name (SKUV, 0x1) // Set SKU Version to 1 + +//Audio Drivers +// Include("audio.asl") + + // + // Storage - UFS/SD + // + Include("ufs.asl") + // Include("sdc.asl") // No SD support on polaris + + // + // ASL Bridge Device + // + // Include("abd.asl") + + Name (ESNL, 20) // Exsoc name limit 20 characters + Name (DBFL, 23) // buffer Length, should be ESNL+3 + +// +// PMIC driver +// +// Include("pmic_core.asl") + +// +// PMICTCC driver +// +// Include("pmic_batt.asl") + + // Include("pep.asl") + // Include("bam.asl") + // Include("buses.asl") + + // MPROC Drivers (PIL Driver and Subsystem Drivers) + // Include("win_mproc.asl") + // Include("syscache.asl") + // Include("HoyaSmmu.asl") + // Include("graphics.asl") + + // Include("SCM.asl"); + + // + // SPMI driver + // + // Include("spmi.asl") + + // + // TLMM controller. + // + // Include("qcgpio.asl") + + // Include("pcie.asl") + + // Include("cbsp_mproc.asl") + + // Include("adsprpc.asl") + + // + // RemoteFS + // + // Include("rfs.asl") + + // + // Qualcomm IPA + // Include("ipa.asl") + + // Include("gsi.asl") + + // Include("qcdb.asl") + + // copied from sm7325, need to check + Include("Pep_lpi.asl") + +// QUPV3 GPI device node and resources +// +// Include("qgpi.asl") diff --git a/Platform/Xiaomi/sm8250/AcpiTables/lmi/ufs.asl b/Platform/Xiaomi/sm8250/AcpiTables/lmi/ufs.asl new file mode 100644 index 000000000..2672f59bf --- /dev/null +++ b/Platform/Xiaomi/sm8250/AcpiTables/lmi/ufs.asl @@ -0,0 +1,40 @@ +// UFS Controller +Device (UFS0) +{ + Method(_STA, 0) + { + Return (0xF) // Set to 0xF to enable + } + + Name (_HID, "QCOM24A5") + Alias(\_SB.EMUL, EMUL) + Name (_UID, 0) + // Check: Cache coherent? + Name (_CCA, 0) + + Method (_CRS, 0x0, NotSerialized) { + Name (RBUF, ResourceTemplate () + { + // UFS register address space + Memory32Fixed (ReadWrite, 0x1D84000, 0x1C000) + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {297} + }) + Return (RBUF) + } + + // UFS Device + Device (DEV0) + { + // Memory Type + Method (_ADR) + { + Return (8) + } + + // Non-removable + Method (_RMV) + { + Return (0) + } + } +} diff --git a/Platform/Xiaomi/sm8250/FdtBlob_compat/elish.dtb b/Platform/Xiaomi/sm8250/FdtBlob_compat/elish.dtb index 9aa30a7bb..1547bff68 100644 Binary files a/Platform/Xiaomi/sm8250/FdtBlob_compat/elish.dtb and b/Platform/Xiaomi/sm8250/FdtBlob_compat/elish.dtb differ diff --git a/Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb b/Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb new file mode 100644 index 000000000..567c0781c Binary files /dev/null and b/Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb differ diff --git a/Platform/Xiaomi/sm8250/FdtBlob_compat/pipa.dtb b/Platform/Xiaomi/sm8250/FdtBlob_compat/pipa.dtb new file mode 100644 index 000000000..462b6eee9 Binary files /dev/null and b/Platform/Xiaomi/sm8250/FdtBlob_compat/pipa.dtb differ diff --git a/Platform/Xiaomi/sm8250/Library/alioth/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Platform/Xiaomi/sm8250/Library/alioth/PlatformMemoryMapLib/PlatformMemoryMapLib.c index 43c7f1034..5dac47198 100644 --- a/Platform/Xiaomi/sm8250/Library/alioth/PlatformMemoryMapLib/PlatformMemoryMapLib.c +++ b/Platform/Xiaomi/sm8250/Library/alioth/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -4,27 +4,29 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { /* Hypervisor seems needed for windows boot? */ {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, - {"HLOS 1", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"AOP", 0x80700000, 0x00160000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, {"XBL Log Buffer", 0x80880000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"HLOS 2", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, {"Removed Mem", 0x80b00000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, {"PIL Reserved", 0x86200000, 0x05D00000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 3", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"Display Reserved", 0x9C000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, {"DBI Dump", 0x9E400000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 4", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - {"HLOS 5", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - - {"HLOS 6", 0xA0000000, 0x1CC00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + {"RAM Partition", 0xA0000000, 0x10000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"PSTORE", 0xB0000000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0xB0190000, 0x0FE70000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"DXE Heap", 0xC0000000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, diff --git a/Platform/Xiaomi/sm8250/Library/elish/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Platform/Xiaomi/sm8250/Library/elish/PlatformMemoryMapLib/PlatformMemoryMapLib.c index 43c7f1034..66b640270 100644 --- a/Platform/Xiaomi/sm8250/Library/elish/PlatformMemoryMapLib/PlatformMemoryMapLib.c +++ b/Platform/Xiaomi/sm8250/Library/elish/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -2,30 +2,29 @@ #include static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { - /* Hypervisor seems needed for windows boot? */ - {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, - {"HLOS 1", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - {"AOP", 0x80700000, 0x00160000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"IPC SHM", 0x805D0000, 0x00020000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"MPSS EFS", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"BOOT INFO", 0x80700000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - {"XBL Log Buffer", 0x80880000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"HLOS 2", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"XBL Log Buffer", 0x80884000, 0x00010000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - {"Removed Mem", 0x80b00000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, - {"PIL Reserved", 0x86200000, 0x05D00000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 3", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"TZApps Reserved", 0x82400000, 0x03A00000, HobOnlyNoCacheSetting, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"PIL Reserved", 0x86000000, 0x0D200000, AddMem, SYS_MEM, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"DXE Heap", 0x98900000, 0x03300000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Sched Heap", 0x9BC00000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"Display Reserved", 0x9C000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, {"DBI Dump", 0x9E400000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 4", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"FV Region", 0x9F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"ABOOT FV", 0x9FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"UEFI FD", 0x9FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - {"HLOS 5", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"HLOS 6", 0xA0000000, 0x1CC00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - + {"Kernel", 0xA0000000, 0x10000000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, {"DXE Heap", 0xC0000000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, diff --git a/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..5dac47198 --- /dev/null +++ b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,68 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { + /* Hypervisor seems needed for windows boot? */ + {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"RAM Partition", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"AOP", 0x80700000, 0x00160000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"XBL Log Buffer", 0x80880000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"Removed Mem", 0x80b00000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"PIL Reserved", 0x86200000, 0x05D00000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x9C000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"DBI Dump", 0x9E400000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + + {"RAM Partition", 0xA0000000, 0x10000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"PSTORE", 0xB0000000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0xB0190000, 0x0FE70000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + {"DXE Heap", 0xC0000000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + + {"RAM Partition", 0xD0000000,0x130000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + /* Other memory regions */ + {"IMEM Base", 0x14680000, 0x00040000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x146BF000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + /* Register regions */ + {"IPC_ROUTER_TOP", 0x00400000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_2_GSI", 0x00800000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x00900000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x00A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x00790000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TCSR_TCSR_REGS", 0x01FC0000, 0x00030000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x02C7D000, 0x00002000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x02C90000, 0x0000A000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_SSC_GSI", 0x05A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x08800000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x0A600000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB_RUMI", 0x0A720000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_SEC", 0x0A800000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"AOSS", 0x0B000000, 0x04000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x0F100000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x0F500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_NORTH", 0x0F900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_HM", 0x17800000, 0x0d981000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"Terminator", 0, 0, 0, 0, 0, 0, 0} +}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} diff --git a/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Platform/Xiaomi/sm8250/Library/lmi/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Platform/Xiaomi/sm8250/Library/pipa/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Platform/Xiaomi/sm8250/Library/pipa/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..65749dce1 --- /dev/null +++ b/Platform/Xiaomi/sm8250/Library/pipa/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,69 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { + /* Hypervisor seems needed for windows boot? */ + {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"HLOS 1", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"AOP", 0x80700000, 0x00160000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"XBL Log Buffer", 0x80880000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"HLOS 2", 0x80894000, 0x0006C000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"Removed Mem", 0x80b00000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"PIL Reserved", 0x86200000, 0x05D00000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 3", 0x8BF00000, 0x10100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x9C000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"DBI Dump", 0x9E400000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 4", 0x9F300000, 0x00C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"HLOS 5", 0x9FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + + {"HLOS 6", 0xA0000000, 0x10000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + {"PSTORE", 0xB0000000, 0x00500000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"HLOS 7", 0xB0400000, 0x0C800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + {"DXE Heap", 0xC0000000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + + {"RAM Partition", 0xD0000000,0x130000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + /* Other memory regions */ + {"IMEM Base", 0x14680000, 0x00040000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x146BF000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + /* Register regions */ + {"IPC_ROUTER_TOP", 0x00400000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_2_GSI", 0x00800000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x00900000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x00A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x00790000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TCSR_TCSR_REGS", 0x01FC0000, 0x00030000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x02C7D000, 0x00002000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x02C90000, 0x0000A000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_SSC_GSI", 0x05A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x08800000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x0A600000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB_RUMI", 0x0A720000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_SEC", 0x0A800000, 0x0011B000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"AOSS", 0x0B000000, 0x04000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x0F100000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x0F500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_NORTH", 0x0F900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_HM", 0x17800000, 0x0d981000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"Terminator", 0, 0, 0, 0, 0, 0, 0} +}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} diff --git a/Platform/Xiaomi/sm8250/Library/pipa/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Platform/Xiaomi/sm8250/Library/pipa/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Platform/Xiaomi/sm8250/Library/pipa/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Platform/Xiaomi/sm8250/elish.dsc b/Platform/Xiaomi/sm8250/elish.dsc index b2816fdcb..29ac362d2 100644 --- a/Platform/Xiaomi/sm8250/elish.dsc +++ b/Platform/Xiaomi/sm8250/elish.dsc @@ -14,7 +14,7 @@ !include Platform/Qualcomm/sm8250/sm8250.dsc [BuildOptions.common] - GCC:*_*_AARCH64_CC_FLAGS = -DMEMMAP_XIAOMI_HACKS -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT [PcdsFixedAtBuild.common] gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1600 diff --git a/Platform/Xiaomi/sm8250/lmi.dsc b/Platform/Xiaomi/sm8250/lmi.dsc new file mode 100644 index 000000000..7040cab2a --- /dev/null +++ b/Platform/Xiaomi/sm8250/lmi.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = lmi + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8250/sm8250.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm8250/lmi.fdf.inc + +!include Platform/Qualcomm/sm8250/sm8250.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT -DENABLE_LINUX_SIMPLE_MASS_STORAGE + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2400 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|420 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Poco F2" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"lmi" diff --git a/Platform/Xiaomi/sm8250/lmi.fdf.inc b/Platform/Xiaomi/sm8250/lmi.fdf.inc new file mode 100644 index 000000000..f72256396 --- /dev/null +++ b/Platform/Xiaomi/sm8250/lmi.fdf.inc @@ -0,0 +1,22 @@ +// per-device BSP DXEs +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8250/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/alioth/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} + +// ACPI Tables +FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { + SECTION RAW = Platform/Xiaomi/sm8250/AcpiTables/alioth/DSDT.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Madt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Madt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Facp.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/Gtdt.aml + SECTION RAW = Silicon/Qualcomm/sm8250/AcpiTables/bgrt.aml + SECTION UI = "AcpiTables" +} + +// Mainline device tree blob +FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { + SECTION RAW = Platform/Xiaomi/sm8250/FdtBlob_compat/lmi.dtb +} diff --git a/Platform/Xiaomi/sm8250/pipa.dsc b/Platform/Xiaomi/sm8250/pipa.dsc new file mode 100644 index 000000000..c4e5f0304 --- /dev/null +++ b/Platform/Xiaomi/sm8250/pipa.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = pipa + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8250/sm8250.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm8250/pipa.fdf.inc + +!include Platform/Qualcomm/sm8250/sm8250.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1800 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2880 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|309 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Mi Pad 6" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"pipa" diff --git a/Platform/Xiaomi/sm8250/pipa.fdf.inc b/Platform/Xiaomi/sm8250/pipa.fdf.inc new file mode 100644 index 000000000..91bad7808 --- /dev/null +++ b/Platform/Xiaomi/sm8250/pipa.fdf.inc @@ -0,0 +1,6 @@ +// per-device BSP DXEs +FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { + SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/sm8250/ButtonsDxe/ButtonsDxe.depex + SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/pipa/ButtonsDxe/ButtonsDxe.efi + SECTION UI = "ButtonsDxe" +} diff --git a/Platform/Xiaomi/sm8475/FdtBlob_compat/yudi.dtb b/Platform/Xiaomi/sm8475/FdtBlob_compat/yudi.dtb new file mode 100644 index 000000000..f9f2d7abd Binary files /dev/null and b/Platform/Xiaomi/sm8475/FdtBlob_compat/yudi.dtb differ diff --git a/Platform/Xiaomi/sm8475/yudi.dsc b/Platform/Xiaomi/sm8475/yudi.dsc new file mode 100644 index 000000000..bffcef74f --- /dev/null +++ b/Platform/Xiaomi/sm8475/yudi.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = yudi + PLATFORM_GUID = 6eaa81ea-98c3-6d92-de4a-4b1c3dd714c2 + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8475/sm8475.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm8475/yudi.fdf.inc + +!include Platform/Qualcomm/sm8475/sm8475.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|2880 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|1800 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|426 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Pad 6 Max 14" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"yudi" diff --git a/Platform/Xiaomi/sm8475/yudi.fdf.inc b/Platform/Xiaomi/sm8475/yudi.fdf.inc new file mode 100644 index 000000000..09f61802e --- /dev/null +++ b/Platform/Xiaomi/sm8475/yudi.fdf.inc @@ -0,0 +1,23 @@ +// per-device BSP DXEs +# FILE DRIVER = 5bd181db-0487-4f1a-ae73-820e165611b3 { +# SECTION DXE_DEPEX = Platform/EFI_Binaries/Drivers/Devices/nx729j/ButtonsDxe/ButtonsDxe.depex +# SECTION PE32 = Platform/EFI_Binaries/Drivers/Devices/nx729j/ButtonsDxe/ButtonsDxe.efi +# SECTION UI = "ButtonsDxe" +# } + +// ACPI Tables +# FILE FREEFORM = 7E374E25-8E01-4FEE-87F2-390C23C606CD { +# SECTION RAW = Silicon/Qualcomm/sm8475/AcpiTables/DBG2.aml +# SECTION RAW = Platform/Nubia/sm8475/AcpiTables/nx729j/DSDT.AML +# SECTION RAW = Silicon/Qualcomm/sm8475/AcpiTables/MADT.aml +# SECTION RAW = Silicon/Qualcomm/sm8475/AcpiTables/FADT.aml +# SECTION RAW = Silicon/Qualcomm/sm8475/AcpiTables/GTDT.aml +# SECTION RAW = Silicon/Qualcomm/sm8475/AcpiTables/IORT.aml +# SECTION RAW = Silicon/Qualcomm/sm8475/AcpiTables/PPTT.aml +# SECTION UI = "AcpiTables" +# } + +// Mainline device tree blob +# FILE FREEFORM = 25462CDA-221F-47DF-AC1D-259CFAA4E326 { +# SECTION RAW = Platform/Qualcomm/sm8475/FdtBlob/sm8475-generic-msd.dtb +# } diff --git a/Platform/Xiaomi/sm8550/FdtBlob_compat/fuxi.dtb b/Platform/Xiaomi/sm8550/FdtBlob_compat/fuxi.dtb new file mode 100644 index 000000000..844a988fd Binary files /dev/null and b/Platform/Xiaomi/sm8550/FdtBlob_compat/fuxi.dtb differ diff --git a/Platform/Xiaomi/sm8550/fuxi.dsc b/Platform/Xiaomi/sm8550/fuxi.dsc new file mode 100644 index 000000000..5c5872155 --- /dev/null +++ b/Platform/Xiaomi/sm8550/fuxi.dsc @@ -0,0 +1,28 @@ +[Defines] + VENDOR_NAME = Xiaomi + PLATFORM_NAME = fuxi + PLATFORM_GUID = 28f1a3bf-193a-47e3-a7b9-5a435eaab2ee + PLATFORM_VERSION = 0.1 + DSC_SPECIFICATION = 0x00010019 + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME) + SUPPORTED_ARCHITECTURES = AARCH64 + BUILD_TARGETS = DEBUG|RELEASE + SKUID_IDENTIFIER = DEFAULT + FLASH_DEFINITION = Platform/Qualcomm/sm8550/sm8550.fdf + DEVICE_DXE_FV_COMPONENTS = Platform/Xiaomi/sm8550/fuxi.fdf.inc + +!include Platform/Qualcomm/sm8550/sm8550.dsc + +[BuildOptions.common] + GCC:*_*_AARCH64_CC_FLAGS = -DENABLE_SIMPLE_INIT + +[PcdsFixedAtBuild.common] + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth|1080 + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight|2400 + + # Simple Init + gSimpleInitTokenSpaceGuid.PcdGuiDefaultDPI|414 + + gRenegadePkgTokenSpaceGuid.PcdDeviceVendor|"Xiaomi" + gRenegadePkgTokenSpaceGuid.PcdDeviceProduct|"Mi 13" + gRenegadePkgTokenSpaceGuid.PcdDeviceCodeName|"fuxi" diff --git a/Platform/Xiaomi/sm8550/fuxi.fdf.inc b/Platform/Xiaomi/sm8550/fuxi.fdf.inc new file mode 100644 index 000000000..e69de29bb diff --git a/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.c b/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.c index 306bfb534..4039b75d7 100644 --- a/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.c +++ b/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.c @@ -10,6 +10,8 @@ #include #include "Library/FrameBufferSerialPortLib.h" +#include + FBCON_POSITION m_Position; FBCON_POSITION m_MaxPosition; @@ -20,6 +22,7 @@ UINTN gWidth = FixedPcdGet32(PcdMipiFrameBufferWidth); // Reserve half screen for output UINTN gHeight = FixedPcdGet32(PcdMipiFrameBufferHeight); UINTN gBpp = FixedPcdGet32(PcdMipiFrameBufferPixelBpp); +UINTN delay = FixedPcdGet32(PcdMipiFrameBufferDelay); // Module-used internal routine void FbConPutCharWithFactor(char c, int type, unsigned scale_factor); @@ -142,6 +145,7 @@ void FbConPutCharWithFactor(char c, int type, unsigned scale_factor) return; newline: + MicroSecondDelay( delay ); m_Position.y += scale_factor; m_Position.x = 0; if (m_Position.y >= m_MaxPosition.y - scale_factor) { diff --git a/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.inf b/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.inf index cd6c385d4..f8c8e4552 100644 --- a/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.inf +++ b/Silicon/Qualcomm/QcomPkg/Library/FrameBufferSerialPortLib/FrameBufferSerialPortLib.inf @@ -28,9 +28,11 @@ HobLib CompilerIntrinsicsLib CacheMaintenanceLib + TimerLib [Pcd] gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight gQcomTokenSpaceGuid.PcdMipiFrameBufferPixelBpp + gQcomTokenSpaceGuid.PcdMipiFrameBufferDelay diff --git a/Silicon/Qualcomm/QcomPkg/QcomPkg.dec b/Silicon/Qualcomm/QcomPkg/QcomPkg.dec index 4cca70797..3c9ec509c 100755 --- a/Silicon/Qualcomm/QcomPkg/QcomPkg.dec +++ b/Silicon/Qualcomm/QcomPkg/QcomPkg.dec @@ -51,6 +51,8 @@ gQcomTokenSpaceGuid.PcdMipiFrameBufferPixelBpp|32|UINT32|0x0000a403 gQcomTokenSpaceGuid.PcdMipiFrameBufferVisibleWidth|1080|UINT32|0x0000a404 gQcomTokenSpaceGuid.PcdMipiFrameBufferVisibleHeight|2160|UINT32|0x0000a405 + gQcomTokenSpaceGuid.PcdMipiFrameBufferDelay|1|UINT32|0x0000a406 + # Touch Screen gQcomTokenSpaceGuid.PcdTouchCtlrAddress|0|UINT16|0x0000a501 gQcomTokenSpaceGuid.PcdTouchCtlrResetPin|0|UINT32|0x0000a502 diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml new file mode 100644 index 000000000..68703c947 Binary files /dev/null and b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.aml differ diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/FADT.dsl b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.dsl new file mode 100644 index 000000000..ddbf2a406 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/AcpiTables/FADT.dsl @@ -0,0 +1,164 @@ +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000114 +[008h 0008 1] Revision : 06 +[009h 0009 1] Checksum : 25 +[00Ah 0010 6] Oem ID : "QCOM " +[010h 0016 8] Oem Table ID : "QCOMEDK2" +[018h 0024 4] Oem Revision : 00006225 +[01Ch 0028 4] Asl Compiler ID : "INTL" +[020h 0032 4] Asl Compiler Revision : 20200925 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 08 [Tablet] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00300000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 03 [EmbeddedControl] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 03 [DWord Access:32] +[078h 0120 8] Address : 00000000009020B4 + +[080h 0128 1] Value to cause reset : 01 +[081h 0129 2] ARM Flags (decoded below) : 0001 + PSCI Compliant : 1 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +[10Ch 0268 8] Hypervisor ID : 000000004D4F4351 \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml new file mode 100644 index 000000000..e5731bd7c Binary files /dev/null and b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.aml differ diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.dsl b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.dsl new file mode 100644 index 000000000..6100a05e0 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/AcpiTables/GTDT.dsl @@ -0,0 +1,63 @@ +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 0000009C +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 91 +[00Ah 0010 6] Oem ID : "QCOM " +[010h 0016 8] Oem Table ID : "QCOMEDK2" +[018h 0024 4] Oem Revision : 00006225 +[01Ch 0028 4] Asl Compiler ID : "INTL" +[020h 0032 4] Asl Compiler Revision : 20200925 + +[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 00000011 +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 00000012 +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[040h 0064 4] Virtual Timer Interrupt : 00000013 +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 00000010 +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF + +[058h 0088 4] Platform Timer Count : 00000001 +[05Ch 0092 4] Platform Timer Offset : 00000060 + +[060h 0096 1] Subtable Type : 00 [Generic Timer Block] +[061h 0097 2] Length : 003C +[063h 0099 1] Reserved : 00 +[064h 0100 8] Block Address : 000000000F120000 +[06Ch 0108 4] Timer Count : 00000001 +[070h 0112 4] Timer Offset : 00000014 + +[074h 0116 1] Frame Number : 00 +[075h 0117 3] Reserved : 000000 +[078h 0120 8] Base Address : 000000000F121000 +[080h 0128 8] EL0 Base Address : 000000000F122000 +[088h 0136 4] Timer Interrupt : 00000028 +[08Ch 0140 4] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[090h 0144 4] Virtual Timer Interrupt : 00000027 +[094h 0148 4] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[098h 0152 4] Common Flags (decoded below) : 00000002 + Secure : 0 + Always On : 1 \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml new file mode 100644 index 000000000..d027d5c91 Binary files /dev/null and b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.aml differ diff --git a/Silicon/Qualcomm/sm6225/AcpiTables/MADT.dsl b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.dsl new file mode 100644 index 000000000..c70f6b92f --- /dev/null +++ b/Silicon/Qualcomm/sm6225/AcpiTables/MADT.dsl @@ -0,0 +1,212 @@ +[000h 0000 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 004h] Table Length : 000002EC +[008h 0008 001h] Revision : 05 +[009h 0009 001h] Checksum : 1A +[00Ah 0010 006h] Oem ID : "QCOM " +[010h 0016 008h] Oem Table ID : "QCOMEDK2" +[018h 0024 004h] Oem Revision : 00006225 +[01Ch 0028 004h] Asl Compiler ID : "INTL" +[020h 0032 004h] Asl Compiler Revision : 20230628 + +[024h 0036 004h] Local Apic Address : 00000000 +[028h 0040 004h] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 001h] Subtable Type : 0B [Generic Interrupt Controller] +[02Dh 0045 001h] Length : 50 +[02Eh 0046 002h] Reserved : 0000 +[030h 0048 004h] CPU Interface Number : 00000000 +[034h 0052 004h] Processor UID : 00000000 +[038h 0056 004h] Flags (decoded below) : 00000001 + Processor Enabled : 0 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[03Ch 0060 004h] Parking Protocol Version : 00000000 +[040h 0064 004h] Performance Interrupt : 00000016 +[044h 0068 008h] Parked Address : 0000000000000000 +[04Ch 0076 008h] Base Address : 0000000000000000 +[054h 0084 008h] Virtual GIC Base Address : 0000000000000000 +[05Ch 0092 008h] Hypervisor GIC Base Address : 0000000000000000 +[064h 0100 004h] Virtual GIC Interrupt : 00000018 +[068h 0104 008h] Redistributor Base Address : 0000000000000000 +[070h 0112 008h] ARM MPIDR : 0000000000000000 +[078h 0120 001h] Efficiency Class : 00 +[079h 0121 001h] Reserved : 00 +[07Ah 0122 002h] SPE Overflow Interrupt : 0000 +[07Ch 0124 002h] TRBE Interrupt : 500B + +[07Eh 0126 001h] Subtable Type : 0B [Generic Interrupt Controller] +[07Fh 0127 001h] Length : 50 +[080h 0128 002h] Reserved : 0000 +[082h 0130 004h] CPU Interface Number : 00000001 +[086h 0134 004h] Processor UID : 00000001 +[08Ah 0138 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[08Eh 0142 004h] Parking Protocol Version : 00000000 +[092h 0146 004h] Performance Interrupt : 00000016 +[096h 0150 008h] Parked Address : 0000000000000000 +[09Eh 0158 008h] Base Address : 0000000000000000 +[0A6h 0166 008h] Virtual GIC Base Address : 0000000000000000 +[0AEh 0174 008h] Hypervisor GIC Base Address : 0000000000000000 +[0B6h 0182 004h] Virtual GIC Interrupt : 00000018 +[0BAh 0186 008h] Redistributor Base Address : 0000000000000000 +[0C2h 0194 008h] ARM MPIDR : 0000000000000001 +[0CAh 0202 001h] Efficiency Class : 00 +[0CBh 0203 001h] Reserved : 00 +[0CCh 0204 002h] SPE Overflow Interrupt : 0000 +[0CEh 0206 002h] TRBE Interrupt : 500B + +[0D0h 0208 001h] Subtable Type : 0B [Generic Interrupt Controller] +[0D1h 0209 001h] Length : 50 +[0D2h 0210 002h] Reserved : 0000 +[0D4h 0212 004h] CPU Interface Number : 00000002 +[0D8h 0216 004h] Processor UID : 00000002 +[0DCh 0220 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0E0h 0224 004h] Parking Protocol Version : 00000000 +[0E4h 0228 004h] Performance Interrupt : 00000016 +[0E8h 0232 008h] Parked Address : 0000000000000000 +[0F0h 0240 008h] Base Address : 0000000000000000 +[0F8h 0248 008h] Virtual GIC Base Address : 0000000000000000 +[100h 0256 008h] Hypervisor GIC Base Address : 0000000000000000 +[108h 0264 004h] Virtual GIC Interrupt : 00000018 +[10Ch 0268 008h] Redistributor Base Address : 0000000000000000 +[114h 0276 008h] ARM MPIDR : 0000000000000002 +[11Ch 0284 001h] Efficiency Class : 00 +[11Dh 0285 001h] Reserved : 00 +[11Eh 0286 002h] SPE Overflow Interrupt : 0000 +[120h 0288 002h] TRBE Interrupt : 500B + +[122h 0290 001h] Subtable Type : 0B [Generic Interrupt Controller] +[123h 0291 001h] Length : 50 +[124h 0292 002h] Reserved : 0000 +[126h 0294 004h] CPU Interface Number : 00000003 +[12Ah 0298 004h] Processor UID : 00000003 +[12Eh 0302 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[132h 0306 004h] Parking Protocol Version : 00000000 +[136h 0310 004h] Performance Interrupt : 00000016 +[13Ah 0314 008h] Parked Address : 0000000000000000 +[142h 0322 008h] Base Address : 0000000000000000 +[14Ah 0330 008h] Virtual GIC Base Address : 0000000000000000 +[152h 0338 008h] Hypervisor GIC Base Address : 0000000000000000 +[15Ah 0346 004h] Virtual GIC Interrupt : 00000018 +[15Eh 0350 008h] Redistributor Base Address : 0000000000000000 +[166h 0358 008h] ARM MPIDR : 0000000000000003 +[16Eh 0366 001h] Efficiency Class : 00 +[16Fh 0367 001h] Reserved : 00 +[170h 0368 002h] SPE Overflow Interrupt : 0000 +[172h 0370 002h] TRBE Interrupt : 500B + +[174h 0372 001h] Subtable Type : 0B [Generic Interrupt Controller] +[175h 0373 001h] Length : 50 +[176h 0374 002h] Reserved : 0000 +[178h 0376 004h] CPU Interface Number : 00000004 +[17Ch 0380 004h] Processor UID : 00000004 +[180h 0384 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[184h 0388 004h] Parking Protocol Version : 00000000 +[188h 0392 004h] Performance Interrupt : 00000016 +[18Ch 0396 008h] Parked Address : 0000000000000000 +[194h 0404 008h] Base Address : 0000000000000000 +[19Ch 0412 008h] Virtual GIC Base Address : 0000000000000000 +[1A4h 0420 008h] Hypervisor GIC Base Address : 0000000000000000 +[1ACh 0428 004h] Virtual GIC Interrupt : 00000018 +[1B0h 0432 008h] Redistributor Base Address : 0000000000000000 +[1B8h 0440 008h] ARM MPIDR : 0000000000000100 +[1C0h 0448 001h] Efficiency Class : 01 +[1C1h 0449 001h] Reserved : 00 +[1C2h 0450 002h] SPE Overflow Interrupt : 0000 +[1C4h 0452 002h] TRBE Interrupt : 500B + +[1C6h 0454 001h] Subtable Type : 0B [Generic Interrupt Controller] +[1C7h 0455 001h] Length : 50 +[1C8h 0456 002h] Reserved : 0000 +[1CAh 0458 004h] CPU Interface Number : 00000005 +[1CEh 0462 004h] Processor UID : 00000005 +[1D2h 0466 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[1D6h 0470 004h] Parking Protocol Version : 00000000 +[1DAh 0474 004h] Performance Interrupt : 00000016 +[1DEh 0478 008h] Parked Address : 0000000000000000 +[1E6h 0486 008h] Base Address : 0000000000000000 +[1EEh 0494 008h] Virtual GIC Base Address : 0000000000000000 +[1F6h 0502 008h] Hypervisor GIC Base Address : 0000000000000000 +[1FEh 0510 004h] Virtual GIC Interrupt : 00000018 +[202h 0514 008h] Redistributor Base Address : 0000000000000000 +[20Ah 0522 008h] ARM MPIDR : 0000000000000101 +[212h 0530 001h] Efficiency Class : 01 +[213h 0531 001h] Reserved : 00 +[214h 0532 002h] SPE Overflow Interrupt : 0000 +[216h 0534 002h] TRBE Interrupt : 500B + +[218h 0536 001h] Subtable Type : 0B [Generic Interrupt Controller] +[219h 0537 001h] Length : 50 +[21Ah 0538 002h] Reserved : 0000 +[21Ch 0540 004h] CPU Interface Number : 00000006 +[220h 0544 004h] Processor UID : 00000006 +[224h 0548 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[228h 0552 004h] Parking Protocol Version : 00000000 +[22Ch 0556 004h] Performance Interrupt : 00000016 +[230h 0560 008h] Parked Address : 0000000000000000 +[238h 0568 008h] Base Address : 0000000000000000 +[240h 0576 008h] Virtual GIC Base Address : 0000000000000000 +[248h 0584 008h] Hypervisor GIC Base Address : 0000000000000000 +[250h 0592 004h] Virtual GIC Interrupt : 00000018 +[254h 0596 008h] Redistributor Base Address : 0000000000000000 +[25Ch 0604 008h] ARM MPIDR : 0000000000000102 +[264h 0612 001h] Efficiency Class : 01 +[265h 0613 001h] Reserved : 00 +[266h 0614 002h] SPE Overflow Interrupt : 0000 +[268h 0616 002h] TRBE Interrupt : 500B + +[26Ah 0618 001h] Subtable Type : 0B [Generic Interrupt Controller] +[26Bh 0619 001h] Length : 50 +[26Ch 0620 002h] Reserved : 0000 +[26Eh 0622 004h] CPU Interface Number : 00000007 +[272h 0626 004h] Processor UID : 00000007 +[276h 0630 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[27Ah 0634 004h] Parking Protocol Version : 00000000 +[27Eh 0638 004h] Performance Interrupt : 00000016 +[282h 0642 008h] Parked Address : 0000000000000000 +[28Ah 0650 008h] Base Address : 0000000000000000 +[292h 0658 008h] Virtual GIC Base Address : 0000000000000000 +[29Ah 0666 008h] Hypervisor GIC Base Address : 0000000000000000 +[2A2h 0674 004h] Virtual GIC Interrupt : 00000018 +[2A6h 0678 008h] Redistributor Base Address : 0000000000000000 +[2AEh 0686 008h] ARM MPIDR : 0000000000000103 +[2B6h 0694 001h] Efficiency Class : 01 +[2B7h 0695 001h] Reserved : 00 +[2B8h 0696 002h] SPE Overflow Interrupt : 0000 +[2BAh 0698 002h] TRBE Interrupt : 500C + +[2BCh 0700 001h] Subtable Type : 0C [Generic Interrupt Distributor] +[2BDh 0701 001h] Length : 18 +[2BEh 0702 002h] Reserved : 0000 +[2C0h 0704 004h] Local GIC Hardware ID : 00000000 +[2C4h 0708 008h] Base Address : 000000000F200000 +[2CCh 0716 004h] Interrupt Base : 00000000 +[2D0h 0720 001h] Version : 03 +[2D1h 0721 003h] Reserved : 000000 + +[2D4h 0724 001h] Subtable Type : 0E [Generic Interrupt Redistributor] +[2D5h 0725 001h] Length : 10 +[2D6h 0726 002h] Reserved : 0000 +[2D8h 0728 008h] Base Address : 000000000F300000 +[2E0h 0736 004h] Length : 00100000 diff --git a/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h b/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h new file mode 100644 index 000000000..edb96ba35 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Include/Configuration/DeviceConfigurationMap.h @@ -0,0 +1,47 @@ +#ifndef _DEVICE_CONFIGURATION_MAP_H_ +#define _DEVICE_CONFIGURATION_MAP_H_ + +#define CONFIGURATION_NAME_MAX_LENGTH 64 + +typedef struct { + CHAR8 Name[CONFIGURATION_NAME_MAX_LENGTH]; + UINT64 Value; +} CONFIGURATION_DESCRIPTOR_EX, *PCONFIGURATION_DESCRIPTOR_EX; + +static CONFIGURATION_DESCRIPTOR_EX gDeviceConfigurationDescriptorEx[] = { + {"NumCpusFuseAddr", 0x5C04C}, + {"EnableShell", 0x1}, + {"SharedIMEMBaseAddr", 0x0C125000}, + {"DloadCookieAddr", 0x003D3000}, + {"DloadCookieValue", 0x10}, + {"NumCpus", 8}, + {"NumActiveCores", 8}, + {"MaxLogFileSize", 0x400000}, + {"UefiMemUseThreshold", 0x77}, + {"USBHS1_Config", 0x0}, + {"UsbFnIoRevNum", 0x00010001}, + {"PwrBtnShutdownFlag", 0x0}, + {"Sdc1GpioConfigOn", 0x1E92}, + {"Sdc2GpioConfigOn", 0x1E92}, + {"Sdc1GpioConfigOff", 0xA00}, + {"Sdc2GpioConfigOff", 0xA00}, + {"EnableSDHCSwitch", 0x1}, + {"EnableUfsIOC", 0}, + {"UfsSmmuConfigForOtherBootDev", 1}, + {"SecurityFlag", 0xC4}, + {"TzAppsRegnAddr", 0x61800000}, + {"TzAppsRegnSize", 0x02100000}, + {"TzAppsRegnSizeLowRAM", 0xB00000}, + {"EnableLogFsSyncInRetail", 0x0}, + {"ShmBridgememSize", 0xA00000}, + {"EnableMultiThreading", 1}, + {"MaxCoreCnt", 8}, + {"EarlyInitCoreCnt", 1}, + {"EnableDisplayThread", 1}, + {"EnableUefiSecAppDebugLogDump", 0x1}, + {"AllowNonPersistentVarsInRetail", 0x1}, + {"MinidumpTALoadingCfg", 0x0}, + /* Terminator */ + {"Terminator", 0xFFFFFFFF}}; + +#endif \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c b/Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c new file mode 100644 index 000000000..32bbfc4d4 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c @@ -0,0 +1,41 @@ +/** @file + *MsPlatformDevicesLib - Device specific library. + +Copyright (C) Microsoft Corporation. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +// #include +#include + +#include + +#include +#include +#include + +VOID +EFIAPI +PlatformSetup() +{ + // Allow MPSS and HLOS to access the allocated RFS Shared Memory Region + // Normally this would be done by a driver in Linux + // TODO: Move to a better place! + // RFSLocateAndProtectSharedArea(); + + // Patch ACPI Tables + // PlatformUpdateAcpiTables(); +} diff --git a/Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf b/Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf new file mode 100644 index 000000000..0730adb33 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf @@ -0,0 +1,47 @@ +## @file +# Ms Platform Devices Library +# Ported from SurfaceDuoPkg +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (C) Microsoft Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MsPlatformDevicesLib + FILE_GUID = 2FDF4E63-5AD5-4385-A729-868019B45A91 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = MsPlatformDevicesLib|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION + +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + MsPlatformDevicesLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RenegadePkg/RenegadePkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6225/sm6225.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DevicePathLib + IoLib + UefiBootServicesTableLib + UefiLib + # AslUpdateLib + # RFSProtectionLib + MemoryMapHelperLib + +[Protocols] + gEfiChipInfoProtocolGuid ## CONSUMES + gQcomSMEMProtocolGuid ## CONSUMES + gEfiPlatformInfoProtocolGuid ## CONSUMES diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..f5b5da16d --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,104 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { +/* EFI_RESOURCE_ EFI_RESOURCE_ATTRIBUTE_ EFI_MEMORY_TYPE ARM_REGION_ATTRIBUTE_ + MemLabel(32 Char.), MemBase, MemSize, BuildHob, ResourceType, ResourceAttribute, MemoryType, CacheAttributes +--------------------- DDR --------------------- */ + {"RAM Partition", 0x40000000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Hypervisor", 0x45700000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x45D00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x46000000, 0x00200000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x46200000, 0x04900000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"PIL Reserved", 0x4AB00000, 0x0A400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x54F00000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"DXE Heap", 0x63900000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK}, + {"RAM Partition", 0x67E00000, 0x09B00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"DBI Dump", 0x56700000, 0x00A00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"Sched Heap", 0x57100000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x57500000, 0x04B00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x5C000000, 0x01000000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"LAST LOG", 0x5D000000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x5D400000, 0x02400000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"FV Region", 0x5F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x5FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0x5FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"SEC Heap", 0x5FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x5FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x5FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x5FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x5FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x5FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Info Blk", 0x5FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + //==================================================3GB RAM Setup================================================== + // This RAM parition starts just after Info Blk and ends with DDR Bank 0 + {"RAM Partition", 0x60000000, 0x1E580000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + // DDR Bank 0 end + + // DDR Bank 1 start + {"RAM Partition", 0x80000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + // As RAM starts at 0x80000000 (2GB) and this is a 3GB device, so it must ends at 5GB, then 0x140000000 = 0xC0000000 + 0x80000000 + {"RAM Partition", 0xC0000000,0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +//================================================================================================================= + +//==================================================4GB RAM Setup================================================== + // This RAM parition starts just after Info Blk and ends with DDR Bank 0 + {"RAM Partition", 0x60000000, 0x1DD00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + // DDR Bank 0 end + + // DDR Bank 1 start + {"RAM Partition", 0x80000000, 0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + // As RAM starts at 0x80000000 (2GB) and this is a 4GB device, so it must ends at 6GB, then 0x180000000 = 0x100000000 + 0x80000000 + {"RAM Partition", 0xC0000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +//================================================================================================================= + +//--------------------- Other --------------------- + {"RPM_SS_MSG_RAM", 0x045F0000, 0x00007000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Base", 0x0C100000, 0x00026000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x0C125000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + // Register regions + {"TCSR_TCSR_REGS", 0x003C0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x00500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x00900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_EAST", 0x00D00000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GCC CLK CTL", 0x01400000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PMIC ARB SPMI", 0x01C00000, 0x02800000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MMCX_CPR3", 0x01648000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01B00000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x01B40000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x01B50000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SLP_CNTR", 0x04403000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0", 0x04410000 ,0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0_TM", 0x04411000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PSHOLD", 0x0440B000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x04A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x04C00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"UFS UFS REGS", 0x04800000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x04700000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x04E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x0597D000, 0x0000C000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x05990000, 0x00009000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"VIDEO_CC", 0x05B00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MDSS", 0x05E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"DISP_CC_DISP_CC", 0x05F00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x0C600000, 0x00080000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_WDT_TMR1", 0x0F017000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QTIMER", 0x0F020000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APCS_ALIAS0_GLB", 0x0F111000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_GIC500_GICD", 0x0F200000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_GIC500_GICR", 0x0F300000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"OSM_RAIL", 0x0F520000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_ACTPM_WRAP", 0x0F500000, 0x000B0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB2", 0x01610000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MCCC_MCCC_MSTR", 0x0447D000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + + /* Terminator for MMU */ + {"Terminator", 0, 0, 0, 0, 0, 0, 0}}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.c new file mode 100644 index 000000000..ddfae0c34 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.c @@ -0,0 +1,188 @@ +/** @file + + Copyright (c) 2011-2014, ARM Limited. All rights reserved. + Copyright (c) 2014, Linaro Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include "PlatformPeiLibInternal.h" + +STATIC +EFI_STATUS +CfgGetMemInfoByName( + CHAR8 *RegionName, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions) +{ + return LocateMemoryMapAreaByName(RegionName, MemRegions); +} + +STATIC +EFI_STATUS +CfgGetMemInfoByAddress( + UINT64 RegionBaseAddress, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions) +{ + return LocateMemoryMapAreaByAddress(RegionBaseAddress, MemRegions); +} + +STATIC +EFI_STATUS +CfgGetCfgInfoString(CHAR8 *Key, CHAR8 *Value, UINTN *ValBuffSize) +{ + if (AsciiStriCmp(Key, "OsTypeString") == 0) { + AsciiStrCpyS(Value, *ValBuffSize, "LA"); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +CfgGetCfgInfoVal(CHAR8 *Key, UINT32 *Value) +{ + PCONFIGURATION_DESCRIPTOR_EX ConfigurationDescriptorEx = + gDeviceConfigurationDescriptorEx; + + // Run through each configuration descriptor + while (ConfigurationDescriptorEx->Value != 0xFFFFFFFF) { + if (AsciiStriCmp(Key, ConfigurationDescriptorEx->Name) == 0) { + *Value = (UINT32)(ConfigurationDescriptorEx->Value & 0xFFFFFFFF); + return EFI_SUCCESS; + } + ConfigurationDescriptorEx++; + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +CfgGetCfgInfoVal64(CHAR8 *Key, UINT64 *Value) +{ + PCONFIGURATION_DESCRIPTOR_EX ConfigurationDescriptorEx = + gDeviceConfigurationDescriptorEx; + + // Run through each configuration descriptor + while (ConfigurationDescriptorEx->Value != 0xFFFFFFFF) { + if (AsciiStriCmp(Key, ConfigurationDescriptorEx->Name) == 0) { + *Value = ConfigurationDescriptorEx->Value; + return EFI_SUCCESS; + } + ConfigurationDescriptorEx++; + } + + return EFI_NOT_FOUND; +} + +STATIC +UINTN +SFlush(VOID) { return EFI_SUCCESS; } + +STATIC +UINTN +SControl(IN UINTN Arg, IN UINTN Param) { return EFI_SUCCESS; } + +STATIC +BOOLEAN +SPoll(VOID) { return TRUE; } + +STATIC +UINTN +SDrain(VOID) { return EFI_SUCCESS; } + +STATIC +EFI_STATUS +ShInstallLib(IN CHAR8 *LibName, IN UINT32 LibVersion, IN VOID *LibIntf) +{ + return EFI_SUCCESS; +} + +UefiCfgLibType ConfigLib = {0x00010002, CfgGetMemInfoByName, + CfgGetCfgInfoString, CfgGetCfgInfoVal, + CfgGetCfgInfoVal64, CfgGetMemInfoByAddress}; + +SioPortLibType SioLib = { + 0x00010001, SerialPortRead, SerialPortWrite, SPoll, + SDrain, SFlush, SControl, SerialPortSetAttributes, +}; + +STATIC +EFI_STATUS +ShLoadLib(CHAR8 *LibName, UINT32 LibVersion, VOID **LibIntf) +{ + if (LibIntf == NULL) + return EFI_NOT_FOUND; + + if (AsciiStriCmp(LibName, "UEFI Config Lib") == 0) { + *LibIntf = &ConfigLib; + return EFI_SUCCESS; + } + + if (AsciiStriCmp(LibName, "SerialPort Lib") == 0) { + *LibIntf = &SioLib; + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +ShLibLoaderType ShLib = {0x00010001, ShInstallLib, ShLoadLib}; + +STATIC +VOID BuildMemHobForFv(IN UINT16 Type) +{ + EFI_PEI_HOB_POINTERS HobPtr; + EFI_HOB_FIRMWARE_VOLUME2 *Hob = NULL; + + HobPtr.Raw = GetHobList(); + while ((HobPtr.Raw = GetNextHob(Type, HobPtr.Raw)) != NULL) { + if (Type == EFI_HOB_TYPE_FV2) { + Hob = HobPtr.FirmwareVolume2; + /* Build memory allocation HOB to mark it as BootServicesData */ + BuildMemoryAllocationHob( + Hob->BaseAddress, EFI_SIZE_TO_PAGES(Hob->Length) * EFI_PAGE_SIZE, + EfiBootServicesData); + } + HobPtr.Raw = GET_NEXT_HOB(HobPtr); + } +} + +STATIC GUID gEfiShLibHobGuid = EFI_SHIM_LIBRARY_GUID; +STATIC GUID gEfiInfoBlkHobGuid = EFI_INFORMATION_BLOCK_GUID; + +VOID InstallPlatformHob() +{ + static int initialized = 0; + + if (!initialized) { + UINTN Data = (UINTN)&ShLib; + UINTN Data2 = 0x5FFFF000; // Info Blk + + BuildMemHobForFv(EFI_HOB_TYPE_FV2); + BuildGuidDataHob(&gEfiShLibHobGuid, &Data, sizeof(Data)); + BuildGuidDataHob(&gEfiInfoBlkHobGuid, &Data2, sizeof(Data2)); + + initialized = 1; + } +} + +EFI_STATUS +EFIAPI +PlatformPeim( + VOID + ) +{ + + BuildFvHob(PcdGet64(PcdFvBaseAddress), PcdGet32(PcdFvSize)); + + InstallPlatformHob(); + + return EFI_SUCCESS; +} diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.inf new file mode 100644 index 000000000..4d4b214d9 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLib.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPeiLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F06 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPeiLib + +[Sources] + PlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6225/sm6225.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + MemoryMapHelperLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvSize + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLibInternal.h b/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLibInternal.h new file mode 100644 index 000000000..03b80bec4 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformPeiLib/PlatformPeiLibInternal.h @@ -0,0 +1,87 @@ +#ifndef __PLATFORM_HOB_INTERNAL_H +#define __PLATFORM_HOB_INTERNAL_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// This varies by device +#include + +typedef EFI_STATUS (*GET_CONFIG_STRING)( + CHAR8 *Key, CHAR8 *Value, UINTN *ValBuffSize); +typedef EFI_STATUS (*GET_CONFIG_VAL)(CHAR8 *Key, UINT32 *Value); +typedef EFI_STATUS (*GET_CONFIG_VAL64)(CHAR8 *Key, UINT64 *Value); + +typedef EFI_STATUS (*GET_MEM_INFO_BY_NAME)( + CHAR8 *RegionName, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions); + +typedef EFI_STATUS (*GET_MEM_INFO_BY_ADDRESS)( + UINT64 RegionBaseAddress, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions); + +typedef struct { + UINT32 LibVersion; + GET_MEM_INFO_BY_NAME GetMemInfoByName; + GET_CONFIG_STRING GetCfgInfoString; + GET_CONFIG_VAL GetCfgInfoVal; + GET_CONFIG_VAL64 GetCfgInfoVal64; + GET_MEM_INFO_BY_ADDRESS GetMemInfoByAddress; +} UefiCfgLibType; + +typedef UINTN (*SIO_READ)(OUT UINT8 *Buffer, IN UINTN NumberOfBytes); +typedef UINTN (*SIO_WRITE)(IN UINT8 *Buffer, IN UINTN NumberOfBytes); +typedef BOOLEAN (*SIO_POLL)(VOID); +typedef UINTN (*SIO_DRAIN)(VOID); +typedef UINTN (*SIO_FLUSH)(VOID); +typedef UINTN (*SIO_CONTROL)(IN UINTN Arg, IN UINTN Param); +typedef EFI_STATUS (*SIO_SETATTRIBUTES)( + IN OUT UINT64 *BaudRate, IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, IN OUT EFI_STOP_BITS_TYPE *StopBits); + +typedef struct { + UINT32 LibVersion; + SIO_READ Read; + SIO_WRITE Write; + SIO_POLL Poll; + SIO_DRAIN Drain; + SIO_FLUSH Flush; + SIO_CONTROL Control; + SIO_SETATTRIBUTES SetAttributes; +} SioPortLibType; + +typedef EFI_STATUS (*INSTALL_LIB)( + IN CHAR8 *LibName, IN UINT32 LibVersion, IN VOID *LibIntf); + +typedef EFI_STATUS (*LOAD_LIB)( + IN CHAR8 *LibName, IN UINT32 LibVersion, OUT VOID **LibIntfPtr); + +typedef struct { + UINT32 LoaderVersion; + INSTALL_LIB InstallLib; + LOAD_LIB LoadLib; +} ShLibLoaderType; + +#define EFI_SHIM_LIBRARY_GUID \ + { \ + 0xbedaeabc, 0x5e70, 0x4d66, \ + { \ + 0x97, 0x33, 0x21, 0x3d, 0x07, 0x2b, 0x9d, 0x04 \ + } \ + } + +#define EFI_INFORMATION_BLOCK_GUID \ + { \ + 0x90a49afd, 0x422f, 0x08ae, \ + { \ + 0x96, 0x11, 0xe7, 0x88, 0xd3, 0x80, 0x48, 0x45 \ + } \ + } + +#endif // __PLATFORM_HOB_INTERNAL_H \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformPrePiLib.inf b/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformPrePiLib.inf new file mode 100644 index 000000000..6ee43aa10 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformPrePiLib.inf @@ -0,0 +1,65 @@ +#/** @file +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPrePiLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F07 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPrePiLib + +[Sources] + PlatformUtils.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6225/sm6225.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseLib + DebugLib + IoLib + ExtractGuidedSectionLib + LzmaDecompressLib + PeCoffGetEntryPointLib + PrePiHobListPointerLib + CacheMaintenanceLib + DebugAgentLib + SerialPortLib + MemoryAllocationLib + PrePiMemoryAllocationLib + PerformanceLib + HobLib + CompilerIntrinsicsLib + # Platform-specific libraries + MemoryInitPeiLib + PlatformPeiLib + PlatformPrePiLib + TimerLib + PrintLib + MemoryMapHelperLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[FixedPcd] + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight + gQcomTokenSpaceGuid.PcdMipiFrameBufferPixelBpp + gQcomTokenSpaceGuid.PcdHallSensorPin + gQcomTokenSpaceGuid.PcdHallSensorActiveLow \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformUtils.c b/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformUtils.c new file mode 100644 index 000000000..b6fe9a3bf --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformUtils.c @@ -0,0 +1,42 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformUtils.h" + + +VOID InitializeSharedUartBuffers(VOID) +{ + INTN* pFbConPosition = (INTN*)(FixedPcdGet32(PcdMipiFrameBufferAddress) + (FixedPcdGet32(PcdMipiFrameBufferWidth) * + FixedPcdGet32(PcdMipiFrameBufferHeight) * + FixedPcdGet32(PcdMipiFrameBufferPixelBpp) / 8)); + + *(pFbConPosition + 0) = 0; + *(pFbConPosition + 1) = 0; +} + +VOID UartInit(VOID) +{ + SerialPortInitialize(); + + InitializeSharedUartBuffers(); + + DEBUG((EFI_D_INFO, "\nRenegade Project edk2-msm (AArch64)\n")); + DEBUG( + (EFI_D_INFO, "Firmware version %s built %a %a\n\n", + (CHAR16 *)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__)); +} + +VOID PlatformInitialize() +{ + UartInit(); +} diff --git a/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformUtils.h b/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformUtils.h new file mode 100644 index 000000000..d38d7c490 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/PlatformPrePiLib/PlatformUtils.h @@ -0,0 +1,8 @@ +#ifndef _PLATFORM_UTILS_H_ +#define _PLATFORM_UTILS_H_ + +#include + +VOID PlatformInitialize(); + +#endif /* _PLATFORM_UTILS_H_ */ \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c b/Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c new file mode 100644 index 000000000..97c402a0b --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c @@ -0,0 +1,500 @@ +#include +#include +#include +#include +#include + +/*********************************************************************** + SMBIOS data definition TYPE4 Processor Information +************************************************************************/ +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_a73 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 2400, // MaxSpeed; + 2400, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 7, // PartNumber; + 4, // CoreCount; + 4, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_a53 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 1900, // MaxSpeed; + 1900, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 6, // PartNumber; + 4, // CoreCount; + 4, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +CHAR8 mCpuName[128] = "Qualcomm Snapdragon 680"; + +CHAR8 *mProcessorInfoType4Strings[] = { + "BGA", "Qualcomm", "Snapdragon 680", NULL}; + +/*********************************************************************** + SMBIOS data definition TYPE7 Cache Information +************************************************************************/ +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a73_L1I = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 1, // SocketDesignation String + 0x380, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (Unknown) + // Reserved :6 + 0x0030, // Maximum Size + 0x0030, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorParity, // Error Correction + CacheTypeInstruction, // System Cache Type + CacheAssociativityOther // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a53_L1I = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 1, // SocketDesignation String + 0x380, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (Unknown) + // Reserved :6 + 0x0030, // Maximum Size + 0x0030, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorParity, // Error Correction + CacheTypeInstruction, // System Cache Type + CacheAssociativity2Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings[] = {"L1 Instruction", "L1 Data", "L2", NULL}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a73_L1D = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 2, // SocketDesignation String + 0x180, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0020, // Maximum Size + 0x0020, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction + CacheTypeData, // System Cache Type + CacheAssociativity2Way // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a53_L1D = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 2, // SocketDesignation String + 0x180, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0020, // Maximum Size + 0x0020, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction + CacheTypeData, // System Cache Type + CacheAssociativity4Way // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a73_L2 = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 3, // SocketDesignation String + 0x0181, // Cache Configuration + // Cache Level :3 (L2) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0800, // Maximum Size + 0x0800, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a53_L2 = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 3, // SocketDesignation String + 0x0181, // Cache Configuration + // Cache Level :3 (L2) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0800, // Maximum Size + 0x0800, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; + +/*********************************************************************** + SMBIOS data definition TYPE17 Memory Device Information +************************************************************************/ +SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { + {EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof(SMBIOS_TABLE_TYPE17), 0}, + 0, // MemoryArrayHandle; // Should match SMBIOS_TABLE_TYPE16.Handle, + // initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + 0xFFFE, // MemoryErrorInformationHandle; (not provided) + 64, // TotalWidth; (unknown) + 64, // DataWidth; (unknown) + 0x2000, // Size; // When bit 15 is 0: Size in MB + // When bit 15 is 1: Size in KB, and continues in ExtendedSize + // initialized at runtime, refer to + // PhyMemArrayInfoUpdateSmbiosType16() + MemoryFormFactorRowOfChips, // FormFactor; ///< The + // enumeration value from MEMORY_FORM_FACTOR. + 0, // DeviceSet; + 1, // DeviceLocator String + 2, // BankLocator String + MemoryTypeLpddr4, // MemoryType; ///< The enumeration + // value from MEMORY_DEVICE_TYPE. + { + // TypeDetail; + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 0, // FastPaged :1; + 0, // StaticColumn :1; + 0, // PseudoStatic :1; + 0, // Rambus :1; + 0, // Synchronous :1; + 0, // Cmos :1; + 0, // Edo :1; + 0, // WindowDram :1; + 0, // CacheDram :1; + 0, // Nonvolatile :1; + 0, // Registered :1; + 1, // Unbuffered :1; + 0, // Reserved1 :1; + }, + 2133, // Speed; (unknown) + 2, // Manufacturer String + 0, // SerialNumber String + 0, // AssetTag String + 0, // PartNumber String + 0, // Attributes; (unknown rank) + 0, // ExtendedSize; (since Size < 32GB-1) + 0, // ConfiguredMemoryClockSpeed; (unknown) + 0, // MinimumVoltage; (unknown) + 0, // MaximumVoltage; (unknown) + 0, // ConfiguredVoltage; (unknown) + MemoryTechnologyDram, // MemoryTechnology ///< The + // enumeration value from MEMORY_DEVICE_TECHNOLOGY + {{ + // MemoryOperatingModeCapability + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 1, // VolatileMemory :1; + 0, // ByteAccessiblePersistentMemory :1; + 0, // BlockAccessiblePersistentMemory :1; + 0 // Reserved :10; + }}, + 0, // FirwareVersion + 0, // ModuleManufacturerID (unknown) + 0, // ModuleProductID (unknown) + 0, // MemorySubsystemControllerManufacturerID (unknown) + 0, // MemorySubsystemControllerProductID (unknown) + 0, // NonVolatileSize + 0xFFFFFFFFFFFFFFFFULL, // VolatileSize // initialized at runtime, refer to + // PhyMemArrayInfoUpdateSmbiosType16() + 0, // CacheSize + 0, // LogicalSize (since MemoryType is not + // MemoryTypeLogicalNonVolatileDevice) + 0, // ExtendedSpeed, + 0 // ExtendedConfiguredMemorySpeed +}; +CHAR8 *mMemDevInfoType17Strings[] = {"Builtin", "BANK 0", NULL}; + +VOID RegisterSOCSmbiosInfo( + SMBIOS_LOG_SMBIOS_DATA LogSmbiosData, + EFI_SMBIOS_HANDLE Type16 +){ + EFI_SMBIOS_HANDLE SmbiosHandle; + // TYPE7 Cache Information + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a73_L1I, + mCacheInfoType7Strings, NULL); + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a53_L1I, + mCacheInfoType7Strings, NULL); + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a73_L1D, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a73.L1CacheHandle = (UINT16)SmbiosHandle; + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a53_L1D, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a53.L1CacheHandle = (UINT16)SmbiosHandle; + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a73_L2, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a73.L2CacheHandle = (UINT16)SmbiosHandle; + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a53_L2, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a53.L2CacheHandle = (UINT16)SmbiosHandle; + + // TYPE4 Processor Information + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_a73, + mProcessorInfoType4Strings, NULL); + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_a53, + mProcessorInfoType4Strings, NULL); + + // TYPE17 Memory Device Information + mMemDevInfoType17.MemoryArrayHandle = Type16; + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings, + NULL); +} diff --git a/Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf b/Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf new file mode 100644 index 000000000..28cd13d90 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf @@ -0,0 +1,19 @@ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SOCSmbiosInfoLib + FILE_GUID = 11F9F33F-2C69-460B-9613-79B967F8EFA6 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SOCSmbiosInfoLib + +[Sources] + SOCSmbiosInfo.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6225/sm6225.dec + diff --git a/Silicon/Qualcomm/sm6225/sm6225.dec b/Silicon/Qualcomm/sm6225/sm6225.dec new file mode 100644 index 000000000..9e3606952 --- /dev/null +++ b/Silicon/Qualcomm/sm6225/sm6225.dec @@ -0,0 +1,15 @@ +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = sm6226Pkg + PACKAGE_GUID = 8f169043-4634-42b9-adab-5040f633596c + PACKAGE_VERSION = 1.0 + +[Includes] + Include + +[Guids] + gsm6225PkgTokenSpaceGuid = { 0x99a14446, 0xaad7, 0xe460, {0xb4, 0xe5, 0x1f, 0x79, 0xaa, 0xa4, 0x93, 0xfd } } + +[PcdsFixedAtBuild.common] + + diff --git a/Silicon/Qualcomm/sm6375/AcpiTables/FADT.aml b/Silicon/Qualcomm/sm6375/AcpiTables/FADT.aml new file mode 100644 index 000000000..68703c947 Binary files /dev/null and b/Silicon/Qualcomm/sm6375/AcpiTables/FADT.aml differ diff --git a/Silicon/Qualcomm/sm6375/AcpiTables/FADT.dsl b/Silicon/Qualcomm/sm6375/AcpiTables/FADT.dsl new file mode 100644 index 000000000..ddbf2a406 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/AcpiTables/FADT.dsl @@ -0,0 +1,164 @@ +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000114 +[008h 0008 1] Revision : 06 +[009h 0009 1] Checksum : 25 +[00Ah 0010 6] Oem ID : "QCOM " +[010h 0016 8] Oem Table ID : "QCOMEDK2" +[018h 0024 4] Oem Revision : 00006225 +[01Ch 0028 4] Asl Compiler ID : "INTL" +[020h 0032 4] Asl Compiler Revision : 20200925 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 08 [Tablet] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00300000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 1 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 03 [EmbeddedControl] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 03 [DWord Access:32] +[078h 0120 8] Address : 00000000009020B4 + +[080h 0128 1] Value to cause reset : 01 +[081h 0129 2] ARM Flags (decoded below) : 0001 + PSCI Compliant : 1 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +[10Ch 0268 8] Hypervisor ID : 000000004D4F4351 \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/AcpiTables/GTDT.aml b/Silicon/Qualcomm/sm6375/AcpiTables/GTDT.aml new file mode 100644 index 000000000..e5731bd7c Binary files /dev/null and b/Silicon/Qualcomm/sm6375/AcpiTables/GTDT.aml differ diff --git a/Silicon/Qualcomm/sm6375/AcpiTables/GTDT.dsl b/Silicon/Qualcomm/sm6375/AcpiTables/GTDT.dsl new file mode 100644 index 000000000..6100a05e0 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/AcpiTables/GTDT.dsl @@ -0,0 +1,63 @@ +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 0000009C +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 91 +[00Ah 0010 6] Oem ID : "QCOM " +[010h 0016 8] Oem Table ID : "QCOMEDK2" +[018h 0024 4] Oem Revision : 00006225 +[01Ch 0028 4] Asl Compiler ID : "INTL" +[020h 0032 4] Asl Compiler Revision : 20200925 + +[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 00000011 +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 00000012 +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[040h 0064 4] Virtual Timer Interrupt : 00000013 +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 00000010 +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF + +[058h 0088 4] Platform Timer Count : 00000001 +[05Ch 0092 4] Platform Timer Offset : 00000060 + +[060h 0096 1] Subtable Type : 00 [Generic Timer Block] +[061h 0097 2] Length : 003C +[063h 0099 1] Reserved : 00 +[064h 0100 8] Block Address : 000000000F120000 +[06Ch 0108 4] Timer Count : 00000001 +[070h 0112 4] Timer Offset : 00000014 + +[074h 0116 1] Frame Number : 00 +[075h 0117 3] Reserved : 000000 +[078h 0120 8] Base Address : 000000000F121000 +[080h 0128 8] EL0 Base Address : 000000000F122000 +[088h 0136 4] Timer Interrupt : 00000028 +[08Ch 0140 4] Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[090h 0144 4] Virtual Timer Interrupt : 00000027 +[094h 0148 4] Virtual Timer Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 +[098h 0152 4] Common Flags (decoded below) : 00000002 + Secure : 0 + Always On : 1 \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/AcpiTables/MADT.aml b/Silicon/Qualcomm/sm6375/AcpiTables/MADT.aml new file mode 100644 index 000000000..d027d5c91 Binary files /dev/null and b/Silicon/Qualcomm/sm6375/AcpiTables/MADT.aml differ diff --git a/Silicon/Qualcomm/sm6375/AcpiTables/MADT.dsl b/Silicon/Qualcomm/sm6375/AcpiTables/MADT.dsl new file mode 100644 index 000000000..c70f6b92f --- /dev/null +++ b/Silicon/Qualcomm/sm6375/AcpiTables/MADT.dsl @@ -0,0 +1,212 @@ +[000h 0000 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 004h] Table Length : 000002EC +[008h 0008 001h] Revision : 05 +[009h 0009 001h] Checksum : 1A +[00Ah 0010 006h] Oem ID : "QCOM " +[010h 0016 008h] Oem Table ID : "QCOMEDK2" +[018h 0024 004h] Oem Revision : 00006225 +[01Ch 0028 004h] Asl Compiler ID : "INTL" +[020h 0032 004h] Asl Compiler Revision : 20230628 + +[024h 0036 004h] Local Apic Address : 00000000 +[028h 0040 004h] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 001h] Subtable Type : 0B [Generic Interrupt Controller] +[02Dh 0045 001h] Length : 50 +[02Eh 0046 002h] Reserved : 0000 +[030h 0048 004h] CPU Interface Number : 00000000 +[034h 0052 004h] Processor UID : 00000000 +[038h 0056 004h] Flags (decoded below) : 00000001 + Processor Enabled : 0 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[03Ch 0060 004h] Parking Protocol Version : 00000000 +[040h 0064 004h] Performance Interrupt : 00000016 +[044h 0068 008h] Parked Address : 0000000000000000 +[04Ch 0076 008h] Base Address : 0000000000000000 +[054h 0084 008h] Virtual GIC Base Address : 0000000000000000 +[05Ch 0092 008h] Hypervisor GIC Base Address : 0000000000000000 +[064h 0100 004h] Virtual GIC Interrupt : 00000018 +[068h 0104 008h] Redistributor Base Address : 0000000000000000 +[070h 0112 008h] ARM MPIDR : 0000000000000000 +[078h 0120 001h] Efficiency Class : 00 +[079h 0121 001h] Reserved : 00 +[07Ah 0122 002h] SPE Overflow Interrupt : 0000 +[07Ch 0124 002h] TRBE Interrupt : 500B + +[07Eh 0126 001h] Subtable Type : 0B [Generic Interrupt Controller] +[07Fh 0127 001h] Length : 50 +[080h 0128 002h] Reserved : 0000 +[082h 0130 004h] CPU Interface Number : 00000001 +[086h 0134 004h] Processor UID : 00000001 +[08Ah 0138 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[08Eh 0142 004h] Parking Protocol Version : 00000000 +[092h 0146 004h] Performance Interrupt : 00000016 +[096h 0150 008h] Parked Address : 0000000000000000 +[09Eh 0158 008h] Base Address : 0000000000000000 +[0A6h 0166 008h] Virtual GIC Base Address : 0000000000000000 +[0AEh 0174 008h] Hypervisor GIC Base Address : 0000000000000000 +[0B6h 0182 004h] Virtual GIC Interrupt : 00000018 +[0BAh 0186 008h] Redistributor Base Address : 0000000000000000 +[0C2h 0194 008h] ARM MPIDR : 0000000000000001 +[0CAh 0202 001h] Efficiency Class : 00 +[0CBh 0203 001h] Reserved : 00 +[0CCh 0204 002h] SPE Overflow Interrupt : 0000 +[0CEh 0206 002h] TRBE Interrupt : 500B + +[0D0h 0208 001h] Subtable Type : 0B [Generic Interrupt Controller] +[0D1h 0209 001h] Length : 50 +[0D2h 0210 002h] Reserved : 0000 +[0D4h 0212 004h] CPU Interface Number : 00000002 +[0D8h 0216 004h] Processor UID : 00000002 +[0DCh 0220 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[0E0h 0224 004h] Parking Protocol Version : 00000000 +[0E4h 0228 004h] Performance Interrupt : 00000016 +[0E8h 0232 008h] Parked Address : 0000000000000000 +[0F0h 0240 008h] Base Address : 0000000000000000 +[0F8h 0248 008h] Virtual GIC Base Address : 0000000000000000 +[100h 0256 008h] Hypervisor GIC Base Address : 0000000000000000 +[108h 0264 004h] Virtual GIC Interrupt : 00000018 +[10Ch 0268 008h] Redistributor Base Address : 0000000000000000 +[114h 0276 008h] ARM MPIDR : 0000000000000002 +[11Ch 0284 001h] Efficiency Class : 00 +[11Dh 0285 001h] Reserved : 00 +[11Eh 0286 002h] SPE Overflow Interrupt : 0000 +[120h 0288 002h] TRBE Interrupt : 500B + +[122h 0290 001h] Subtable Type : 0B [Generic Interrupt Controller] +[123h 0291 001h] Length : 50 +[124h 0292 002h] Reserved : 0000 +[126h 0294 004h] CPU Interface Number : 00000003 +[12Ah 0298 004h] Processor UID : 00000003 +[12Eh 0302 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[132h 0306 004h] Parking Protocol Version : 00000000 +[136h 0310 004h] Performance Interrupt : 00000016 +[13Ah 0314 008h] Parked Address : 0000000000000000 +[142h 0322 008h] Base Address : 0000000000000000 +[14Ah 0330 008h] Virtual GIC Base Address : 0000000000000000 +[152h 0338 008h] Hypervisor GIC Base Address : 0000000000000000 +[15Ah 0346 004h] Virtual GIC Interrupt : 00000018 +[15Eh 0350 008h] Redistributor Base Address : 0000000000000000 +[166h 0358 008h] ARM MPIDR : 0000000000000003 +[16Eh 0366 001h] Efficiency Class : 00 +[16Fh 0367 001h] Reserved : 00 +[170h 0368 002h] SPE Overflow Interrupt : 0000 +[172h 0370 002h] TRBE Interrupt : 500B + +[174h 0372 001h] Subtable Type : 0B [Generic Interrupt Controller] +[175h 0373 001h] Length : 50 +[176h 0374 002h] Reserved : 0000 +[178h 0376 004h] CPU Interface Number : 00000004 +[17Ch 0380 004h] Processor UID : 00000004 +[180h 0384 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[184h 0388 004h] Parking Protocol Version : 00000000 +[188h 0392 004h] Performance Interrupt : 00000016 +[18Ch 0396 008h] Parked Address : 0000000000000000 +[194h 0404 008h] Base Address : 0000000000000000 +[19Ch 0412 008h] Virtual GIC Base Address : 0000000000000000 +[1A4h 0420 008h] Hypervisor GIC Base Address : 0000000000000000 +[1ACh 0428 004h] Virtual GIC Interrupt : 00000018 +[1B0h 0432 008h] Redistributor Base Address : 0000000000000000 +[1B8h 0440 008h] ARM MPIDR : 0000000000000100 +[1C0h 0448 001h] Efficiency Class : 01 +[1C1h 0449 001h] Reserved : 00 +[1C2h 0450 002h] SPE Overflow Interrupt : 0000 +[1C4h 0452 002h] TRBE Interrupt : 500B + +[1C6h 0454 001h] Subtable Type : 0B [Generic Interrupt Controller] +[1C7h 0455 001h] Length : 50 +[1C8h 0456 002h] Reserved : 0000 +[1CAh 0458 004h] CPU Interface Number : 00000005 +[1CEh 0462 004h] Processor UID : 00000005 +[1D2h 0466 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[1D6h 0470 004h] Parking Protocol Version : 00000000 +[1DAh 0474 004h] Performance Interrupt : 00000016 +[1DEh 0478 008h] Parked Address : 0000000000000000 +[1E6h 0486 008h] Base Address : 0000000000000000 +[1EEh 0494 008h] Virtual GIC Base Address : 0000000000000000 +[1F6h 0502 008h] Hypervisor GIC Base Address : 0000000000000000 +[1FEh 0510 004h] Virtual GIC Interrupt : 00000018 +[202h 0514 008h] Redistributor Base Address : 0000000000000000 +[20Ah 0522 008h] ARM MPIDR : 0000000000000101 +[212h 0530 001h] Efficiency Class : 01 +[213h 0531 001h] Reserved : 00 +[214h 0532 002h] SPE Overflow Interrupt : 0000 +[216h 0534 002h] TRBE Interrupt : 500B + +[218h 0536 001h] Subtable Type : 0B [Generic Interrupt Controller] +[219h 0537 001h] Length : 50 +[21Ah 0538 002h] Reserved : 0000 +[21Ch 0540 004h] CPU Interface Number : 00000006 +[220h 0544 004h] Processor UID : 00000006 +[224h 0548 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[228h 0552 004h] Parking Protocol Version : 00000000 +[22Ch 0556 004h] Performance Interrupt : 00000016 +[230h 0560 008h] Parked Address : 0000000000000000 +[238h 0568 008h] Base Address : 0000000000000000 +[240h 0576 008h] Virtual GIC Base Address : 0000000000000000 +[248h 0584 008h] Hypervisor GIC Base Address : 0000000000000000 +[250h 0592 004h] Virtual GIC Interrupt : 00000018 +[254h 0596 008h] Redistributor Base Address : 0000000000000000 +[25Ch 0604 008h] ARM MPIDR : 0000000000000102 +[264h 0612 001h] Efficiency Class : 01 +[265h 0613 001h] Reserved : 00 +[266h 0614 002h] SPE Overflow Interrupt : 0000 +[268h 0616 002h] TRBE Interrupt : 500B + +[26Ah 0618 001h] Subtable Type : 0B [Generic Interrupt Controller] +[26Bh 0619 001h] Length : 50 +[26Ch 0620 002h] Reserved : 0000 +[26Eh 0622 004h] CPU Interface Number : 00000007 +[272h 0626 004h] Processor UID : 00000007 +[276h 0630 004h] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[27Ah 0634 004h] Parking Protocol Version : 00000000 +[27Eh 0638 004h] Performance Interrupt : 00000016 +[282h 0642 008h] Parked Address : 0000000000000000 +[28Ah 0650 008h] Base Address : 0000000000000000 +[292h 0658 008h] Virtual GIC Base Address : 0000000000000000 +[29Ah 0666 008h] Hypervisor GIC Base Address : 0000000000000000 +[2A2h 0674 004h] Virtual GIC Interrupt : 00000018 +[2A6h 0678 008h] Redistributor Base Address : 0000000000000000 +[2AEh 0686 008h] ARM MPIDR : 0000000000000103 +[2B6h 0694 001h] Efficiency Class : 01 +[2B7h 0695 001h] Reserved : 00 +[2B8h 0696 002h] SPE Overflow Interrupt : 0000 +[2BAh 0698 002h] TRBE Interrupt : 500C + +[2BCh 0700 001h] Subtable Type : 0C [Generic Interrupt Distributor] +[2BDh 0701 001h] Length : 18 +[2BEh 0702 002h] Reserved : 0000 +[2C0h 0704 004h] Local GIC Hardware ID : 00000000 +[2C4h 0708 008h] Base Address : 000000000F200000 +[2CCh 0716 004h] Interrupt Base : 00000000 +[2D0h 0720 001h] Version : 03 +[2D1h 0721 003h] Reserved : 000000 + +[2D4h 0724 001h] Subtable Type : 0E [Generic Interrupt Redistributor] +[2D5h 0725 001h] Length : 10 +[2D6h 0726 002h] Reserved : 0000 +[2D8h 0728 008h] Base Address : 000000000F300000 +[2E0h 0736 004h] Length : 00100000 diff --git a/Silicon/Qualcomm/sm6375/Include/Configuration/DeviceConfigurationMap.h b/Silicon/Qualcomm/sm6375/Include/Configuration/DeviceConfigurationMap.h new file mode 100644 index 000000000..edb96ba35 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Include/Configuration/DeviceConfigurationMap.h @@ -0,0 +1,47 @@ +#ifndef _DEVICE_CONFIGURATION_MAP_H_ +#define _DEVICE_CONFIGURATION_MAP_H_ + +#define CONFIGURATION_NAME_MAX_LENGTH 64 + +typedef struct { + CHAR8 Name[CONFIGURATION_NAME_MAX_LENGTH]; + UINT64 Value; +} CONFIGURATION_DESCRIPTOR_EX, *PCONFIGURATION_DESCRIPTOR_EX; + +static CONFIGURATION_DESCRIPTOR_EX gDeviceConfigurationDescriptorEx[] = { + {"NumCpusFuseAddr", 0x5C04C}, + {"EnableShell", 0x1}, + {"SharedIMEMBaseAddr", 0x0C125000}, + {"DloadCookieAddr", 0x003D3000}, + {"DloadCookieValue", 0x10}, + {"NumCpus", 8}, + {"NumActiveCores", 8}, + {"MaxLogFileSize", 0x400000}, + {"UefiMemUseThreshold", 0x77}, + {"USBHS1_Config", 0x0}, + {"UsbFnIoRevNum", 0x00010001}, + {"PwrBtnShutdownFlag", 0x0}, + {"Sdc1GpioConfigOn", 0x1E92}, + {"Sdc2GpioConfigOn", 0x1E92}, + {"Sdc1GpioConfigOff", 0xA00}, + {"Sdc2GpioConfigOff", 0xA00}, + {"EnableSDHCSwitch", 0x1}, + {"EnableUfsIOC", 0}, + {"UfsSmmuConfigForOtherBootDev", 1}, + {"SecurityFlag", 0xC4}, + {"TzAppsRegnAddr", 0x61800000}, + {"TzAppsRegnSize", 0x02100000}, + {"TzAppsRegnSizeLowRAM", 0xB00000}, + {"EnableLogFsSyncInRetail", 0x0}, + {"ShmBridgememSize", 0xA00000}, + {"EnableMultiThreading", 1}, + {"MaxCoreCnt", 8}, + {"EarlyInitCoreCnt", 1}, + {"EnableDisplayThread", 1}, + {"EnableUefiSecAppDebugLogDump", 0x1}, + {"AllowNonPersistentVarsInRetail", 0x1}, + {"MinidumpTALoadingCfg", 0x0}, + /* Terminator */ + {"Terminator", 0xFFFFFFFF}}; + +#endif \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c b/Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c new file mode 100644 index 000000000..32bbfc4d4 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c @@ -0,0 +1,41 @@ +/** @file + *MsPlatformDevicesLib - Device specific library. + +Copyright (C) Microsoft Corporation. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +// #include +#include + +#include + +#include +#include +#include + +VOID +EFIAPI +PlatformSetup() +{ + // Allow MPSS and HLOS to access the allocated RFS Shared Memory Region + // Normally this would be done by a driver in Linux + // TODO: Move to a better place! + // RFSLocateAndProtectSharedArea(); + + // Patch ACPI Tables + // PlatformUpdateAcpiTables(); +} diff --git a/Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf b/Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf new file mode 100644 index 000000000..e743a9c9d --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf @@ -0,0 +1,47 @@ +## @file +# Ms Platform Devices Library +# Ported from SurfaceDuoPkg +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (C) Microsoft Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MsPlatformDevicesLib + FILE_GUID = 2FDF4E63-5AD5-4385-A729-868019B45A91 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = MsPlatformDevicesLib|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION + +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + MsPlatformDevicesLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RenegadePkg/RenegadePkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6375/sm6375.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DevicePathLib + IoLib + UefiBootServicesTableLib + UefiLib + # AslUpdateLib + # RFSProtectionLib + MemoryMapHelperLib + +[Protocols] + gEfiChipInfoProtocolGuid ## CONSUMES + gQcomSMEMProtocolGuid ## CONSUMES + gEfiPlatformInfoProtocolGuid ## CONSUMES diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..f5b5da16d --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,104 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { +/* EFI_RESOURCE_ EFI_RESOURCE_ATTRIBUTE_ EFI_MEMORY_TYPE ARM_REGION_ATTRIBUTE_ + MemLabel(32 Char.), MemBase, MemSize, BuildHob, ResourceType, ResourceAttribute, MemoryType, CacheAttributes +--------------------- DDR --------------------- */ + {"RAM Partition", 0x40000000, 0x05700000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Hypervisor", 0x45700000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x45D00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x46000000, 0x00200000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x46200000, 0x04900000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"PIL Reserved", 0x4AB00000, 0x0A400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x54F00000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"DXE Heap", 0x63900000, 0x0E000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK}, + {"RAM Partition", 0x67E00000, 0x09B00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"DBI Dump", 0x56700000, 0x00A00000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"Sched Heap", 0x57100000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x57500000, 0x04B00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0x5C000000, 0x01000000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"LAST LOG", 0x5D000000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x5D400000, 0x02400000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"FV Region", 0x5F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x5FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0x5FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"SEC Heap", 0x5FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x5FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x5FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x5FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x5FFD0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x5FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Info Blk", 0x5FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + //==================================================3GB RAM Setup================================================== + // This RAM parition starts just after Info Blk and ends with DDR Bank 0 + {"RAM Partition", 0x60000000, 0x1E580000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + // DDR Bank 0 end + + // DDR Bank 1 start + {"RAM Partition", 0x80000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + // As RAM starts at 0x80000000 (2GB) and this is a 3GB device, so it must ends at 5GB, then 0x140000000 = 0xC0000000 + 0x80000000 + {"RAM Partition", 0xC0000000,0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +//================================================================================================================= + +//==================================================4GB RAM Setup================================================== + // This RAM parition starts just after Info Blk and ends with DDR Bank 0 + {"RAM Partition", 0x60000000, 0x1DD00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + // DDR Bank 0 end + + // DDR Bank 1 start + {"RAM Partition", 0x80000000, 0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + // As RAM starts at 0x80000000 (2GB) and this is a 4GB device, so it must ends at 6GB, then 0x180000000 = 0x100000000 + 0x80000000 + {"RAM Partition", 0xC0000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +//================================================================================================================= + +//--------------------- Other --------------------- + {"RPM_SS_MSG_RAM", 0x045F0000, 0x00007000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Base", 0x0C100000, 0x00026000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x0C125000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + // Register regions + {"TCSR_TCSR_REGS", 0x003C0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x00500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x00900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_EAST", 0x00D00000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GCC CLK CTL", 0x01400000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PMIC ARB SPMI", 0x01C00000, 0x02800000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MMCX_CPR3", 0x01648000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01B00000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x01B40000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x01B50000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SLP_CNTR", 0x04403000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0", 0x04410000 ,0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0_TM", 0x04411000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PSHOLD", 0x0440B000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_0_GSI", 0x04A00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUPV3_1_GSI", 0x04C00000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"UFS UFS REGS", 0x04800000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x04700000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB30_PRIM", 0x04E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_GMU_CX_BLK", 0x0597D000, 0x0000C000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GPU_CC", 0x05990000, 0x00009000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"VIDEO_CC", 0x05B00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MDSS", 0x05E00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"DISP_CC_DISP_CC", 0x05F00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x0C600000, 0x00080000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_WDT_TMR1", 0x0F017000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QTIMER", 0x0F020000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APCS_ALIAS0_GLB", 0x0F111000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_GIC500_GICD", 0x0F200000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_GIC500_GICR", 0x0F300000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"OSM_RAIL", 0x0F520000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_ACTPM_WRAP", 0x0F500000, 0x000B0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB2", 0x01610000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"MCCC_MCCC_MSTR", 0x0447D000, 0x00001000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + + /* Terminator for MMU */ + {"Terminator", 0, 0, 0, 0, 0, 0, 0}}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.c new file mode 100644 index 000000000..ddfae0c34 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.c @@ -0,0 +1,188 @@ +/** @file + + Copyright (c) 2011-2014, ARM Limited. All rights reserved. + Copyright (c) 2014, Linaro Limited. All rights reserved. + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include +#include "PlatformPeiLibInternal.h" + +STATIC +EFI_STATUS +CfgGetMemInfoByName( + CHAR8 *RegionName, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions) +{ + return LocateMemoryMapAreaByName(RegionName, MemRegions); +} + +STATIC +EFI_STATUS +CfgGetMemInfoByAddress( + UINT64 RegionBaseAddress, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions) +{ + return LocateMemoryMapAreaByAddress(RegionBaseAddress, MemRegions); +} + +STATIC +EFI_STATUS +CfgGetCfgInfoString(CHAR8 *Key, CHAR8 *Value, UINTN *ValBuffSize) +{ + if (AsciiStriCmp(Key, "OsTypeString") == 0) { + AsciiStrCpyS(Value, *ValBuffSize, "LA"); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +CfgGetCfgInfoVal(CHAR8 *Key, UINT32 *Value) +{ + PCONFIGURATION_DESCRIPTOR_EX ConfigurationDescriptorEx = + gDeviceConfigurationDescriptorEx; + + // Run through each configuration descriptor + while (ConfigurationDescriptorEx->Value != 0xFFFFFFFF) { + if (AsciiStriCmp(Key, ConfigurationDescriptorEx->Name) == 0) { + *Value = (UINT32)(ConfigurationDescriptorEx->Value & 0xFFFFFFFF); + return EFI_SUCCESS; + } + ConfigurationDescriptorEx++; + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +CfgGetCfgInfoVal64(CHAR8 *Key, UINT64 *Value) +{ + PCONFIGURATION_DESCRIPTOR_EX ConfigurationDescriptorEx = + gDeviceConfigurationDescriptorEx; + + // Run through each configuration descriptor + while (ConfigurationDescriptorEx->Value != 0xFFFFFFFF) { + if (AsciiStriCmp(Key, ConfigurationDescriptorEx->Name) == 0) { + *Value = ConfigurationDescriptorEx->Value; + return EFI_SUCCESS; + } + ConfigurationDescriptorEx++; + } + + return EFI_NOT_FOUND; +} + +STATIC +UINTN +SFlush(VOID) { return EFI_SUCCESS; } + +STATIC +UINTN +SControl(IN UINTN Arg, IN UINTN Param) { return EFI_SUCCESS; } + +STATIC +BOOLEAN +SPoll(VOID) { return TRUE; } + +STATIC +UINTN +SDrain(VOID) { return EFI_SUCCESS; } + +STATIC +EFI_STATUS +ShInstallLib(IN CHAR8 *LibName, IN UINT32 LibVersion, IN VOID *LibIntf) +{ + return EFI_SUCCESS; +} + +UefiCfgLibType ConfigLib = {0x00010002, CfgGetMemInfoByName, + CfgGetCfgInfoString, CfgGetCfgInfoVal, + CfgGetCfgInfoVal64, CfgGetMemInfoByAddress}; + +SioPortLibType SioLib = { + 0x00010001, SerialPortRead, SerialPortWrite, SPoll, + SDrain, SFlush, SControl, SerialPortSetAttributes, +}; + +STATIC +EFI_STATUS +ShLoadLib(CHAR8 *LibName, UINT32 LibVersion, VOID **LibIntf) +{ + if (LibIntf == NULL) + return EFI_NOT_FOUND; + + if (AsciiStriCmp(LibName, "UEFI Config Lib") == 0) { + *LibIntf = &ConfigLib; + return EFI_SUCCESS; + } + + if (AsciiStriCmp(LibName, "SerialPort Lib") == 0) { + *LibIntf = &SioLib; + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +ShLibLoaderType ShLib = {0x00010001, ShInstallLib, ShLoadLib}; + +STATIC +VOID BuildMemHobForFv(IN UINT16 Type) +{ + EFI_PEI_HOB_POINTERS HobPtr; + EFI_HOB_FIRMWARE_VOLUME2 *Hob = NULL; + + HobPtr.Raw = GetHobList(); + while ((HobPtr.Raw = GetNextHob(Type, HobPtr.Raw)) != NULL) { + if (Type == EFI_HOB_TYPE_FV2) { + Hob = HobPtr.FirmwareVolume2; + /* Build memory allocation HOB to mark it as BootServicesData */ + BuildMemoryAllocationHob( + Hob->BaseAddress, EFI_SIZE_TO_PAGES(Hob->Length) * EFI_PAGE_SIZE, + EfiBootServicesData); + } + HobPtr.Raw = GET_NEXT_HOB(HobPtr); + } +} + +STATIC GUID gEfiShLibHobGuid = EFI_SHIM_LIBRARY_GUID; +STATIC GUID gEfiInfoBlkHobGuid = EFI_INFORMATION_BLOCK_GUID; + +VOID InstallPlatformHob() +{ + static int initialized = 0; + + if (!initialized) { + UINTN Data = (UINTN)&ShLib; + UINTN Data2 = 0x5FFFF000; // Info Blk + + BuildMemHobForFv(EFI_HOB_TYPE_FV2); + BuildGuidDataHob(&gEfiShLibHobGuid, &Data, sizeof(Data)); + BuildGuidDataHob(&gEfiInfoBlkHobGuid, &Data2, sizeof(Data2)); + + initialized = 1; + } +} + +EFI_STATUS +EFIAPI +PlatformPeim( + VOID + ) +{ + + BuildFvHob(PcdGet64(PcdFvBaseAddress), PcdGet32(PcdFvSize)); + + InstallPlatformHob(); + + return EFI_SUCCESS; +} diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.inf new file mode 100644 index 000000000..696703297 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLib.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPeiLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F06 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPeiLib + +[Sources] + PlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6375/sm6375.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + MemoryMapHelperLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvSize + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLibInternal.h b/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLibInternal.h new file mode 100644 index 000000000..03b80bec4 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformPeiLib/PlatformPeiLibInternal.h @@ -0,0 +1,87 @@ +#ifndef __PLATFORM_HOB_INTERNAL_H +#define __PLATFORM_HOB_INTERNAL_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// This varies by device +#include + +typedef EFI_STATUS (*GET_CONFIG_STRING)( + CHAR8 *Key, CHAR8 *Value, UINTN *ValBuffSize); +typedef EFI_STATUS (*GET_CONFIG_VAL)(CHAR8 *Key, UINT32 *Value); +typedef EFI_STATUS (*GET_CONFIG_VAL64)(CHAR8 *Key, UINT64 *Value); + +typedef EFI_STATUS (*GET_MEM_INFO_BY_NAME)( + CHAR8 *RegionName, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions); + +typedef EFI_STATUS (*GET_MEM_INFO_BY_ADDRESS)( + UINT64 RegionBaseAddress, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions); + +typedef struct { + UINT32 LibVersion; + GET_MEM_INFO_BY_NAME GetMemInfoByName; + GET_CONFIG_STRING GetCfgInfoString; + GET_CONFIG_VAL GetCfgInfoVal; + GET_CONFIG_VAL64 GetCfgInfoVal64; + GET_MEM_INFO_BY_ADDRESS GetMemInfoByAddress; +} UefiCfgLibType; + +typedef UINTN (*SIO_READ)(OUT UINT8 *Buffer, IN UINTN NumberOfBytes); +typedef UINTN (*SIO_WRITE)(IN UINT8 *Buffer, IN UINTN NumberOfBytes); +typedef BOOLEAN (*SIO_POLL)(VOID); +typedef UINTN (*SIO_DRAIN)(VOID); +typedef UINTN (*SIO_FLUSH)(VOID); +typedef UINTN (*SIO_CONTROL)(IN UINTN Arg, IN UINTN Param); +typedef EFI_STATUS (*SIO_SETATTRIBUTES)( + IN OUT UINT64 *BaudRate, IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, IN OUT EFI_STOP_BITS_TYPE *StopBits); + +typedef struct { + UINT32 LibVersion; + SIO_READ Read; + SIO_WRITE Write; + SIO_POLL Poll; + SIO_DRAIN Drain; + SIO_FLUSH Flush; + SIO_CONTROL Control; + SIO_SETATTRIBUTES SetAttributes; +} SioPortLibType; + +typedef EFI_STATUS (*INSTALL_LIB)( + IN CHAR8 *LibName, IN UINT32 LibVersion, IN VOID *LibIntf); + +typedef EFI_STATUS (*LOAD_LIB)( + IN CHAR8 *LibName, IN UINT32 LibVersion, OUT VOID **LibIntfPtr); + +typedef struct { + UINT32 LoaderVersion; + INSTALL_LIB InstallLib; + LOAD_LIB LoadLib; +} ShLibLoaderType; + +#define EFI_SHIM_LIBRARY_GUID \ + { \ + 0xbedaeabc, 0x5e70, 0x4d66, \ + { \ + 0x97, 0x33, 0x21, 0x3d, 0x07, 0x2b, 0x9d, 0x04 \ + } \ + } + +#define EFI_INFORMATION_BLOCK_GUID \ + { \ + 0x90a49afd, 0x422f, 0x08ae, \ + { \ + 0x96, 0x11, 0xe7, 0x88, 0xd3, 0x80, 0x48, 0x45 \ + } \ + } + +#endif // __PLATFORM_HOB_INTERNAL_H \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformPrePiLib.inf b/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformPrePiLib.inf new file mode 100644 index 000000000..f047aeb50 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformPrePiLib.inf @@ -0,0 +1,65 @@ +#/** @file +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPrePiLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F07 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPrePiLib + +[Sources] + PlatformUtils.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + ArmPkg/ArmPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6375/sm6375.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseLib + DebugLib + IoLib + ExtractGuidedSectionLib + LzmaDecompressLib + PeCoffGetEntryPointLib + PrePiHobListPointerLib + CacheMaintenanceLib + DebugAgentLib + SerialPortLib + MemoryAllocationLib + PrePiMemoryAllocationLib + PerformanceLib + HobLib + CompilerIntrinsicsLib + # Platform-specific libraries + MemoryInitPeiLib + PlatformPeiLib + PlatformPrePiLib + TimerLib + PrintLib + MemoryMapHelperLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[FixedPcd] + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight + gQcomTokenSpaceGuid.PcdMipiFrameBufferPixelBpp + gQcomTokenSpaceGuid.PcdHallSensorPin + gQcomTokenSpaceGuid.PcdHallSensorActiveLow \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformUtils.c b/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformUtils.c new file mode 100644 index 000000000..b6fe9a3bf --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformUtils.c @@ -0,0 +1,42 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformUtils.h" + + +VOID InitializeSharedUartBuffers(VOID) +{ + INTN* pFbConPosition = (INTN*)(FixedPcdGet32(PcdMipiFrameBufferAddress) + (FixedPcdGet32(PcdMipiFrameBufferWidth) * + FixedPcdGet32(PcdMipiFrameBufferHeight) * + FixedPcdGet32(PcdMipiFrameBufferPixelBpp) / 8)); + + *(pFbConPosition + 0) = 0; + *(pFbConPosition + 1) = 0; +} + +VOID UartInit(VOID) +{ + SerialPortInitialize(); + + InitializeSharedUartBuffers(); + + DEBUG((EFI_D_INFO, "\nRenegade Project edk2-msm (AArch64)\n")); + DEBUG( + (EFI_D_INFO, "Firmware version %s built %a %a\n\n", + (CHAR16 *)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__)); +} + +VOID PlatformInitialize() +{ + UartInit(); +} diff --git a/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformUtils.h b/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformUtils.h new file mode 100644 index 000000000..d38d7c490 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/PlatformPrePiLib/PlatformUtils.h @@ -0,0 +1,8 @@ +#ifndef _PLATFORM_UTILS_H_ +#define _PLATFORM_UTILS_H_ + +#include + +VOID PlatformInitialize(); + +#endif /* _PLATFORM_UTILS_H_ */ \ No newline at end of file diff --git a/Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c b/Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c new file mode 100644 index 000000000..537e939f5 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c @@ -0,0 +1,500 @@ +#include +#include +#include +#include +#include + +/*********************************************************************** + SMBIOS data definition TYPE4 Processor Information +************************************************************************/ +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_a73 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 2400, // MaxSpeed; + 2400, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 7, // PartNumber; + 4, // CoreCount; + 4, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_a53 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 1900, // MaxSpeed; + 1900, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 6, // PartNumber; + 4, // CoreCount; + 4, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +CHAR8 mCpuName[128] = "Qualcomm Snapdragon 695 5G"; + +CHAR8 *mProcessorInfoType4Strings[] = { + "BGA", "Qualcomm", "Snapdragon 695 5G", NULL}; + +/*********************************************************************** + SMBIOS data definition TYPE7 Cache Information +************************************************************************/ +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a73_L1I = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 1, // SocketDesignation String + 0x380, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (Unknown) + // Reserved :6 + 0x0030, // Maximum Size + 0x0030, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorParity, // Error Correction + CacheTypeInstruction, // System Cache Type + CacheAssociativityOther // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a53_L1I = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 1, // SocketDesignation String + 0x380, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (Unknown) + // Reserved :6 + 0x0030, // Maximum Size + 0x0030, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorParity, // Error Correction + CacheTypeInstruction, // System Cache Type + CacheAssociativity2Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings[] = {"L1 Instruction", "L1 Data", "L2", NULL}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a73_L1D = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 2, // SocketDesignation String + 0x180, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0020, // Maximum Size + 0x0020, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction + CacheTypeData, // System Cache Type + CacheAssociativity2Way // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a53_L1D = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 2, // SocketDesignation String + 0x180, // Cache Configuration + // Cache Level :3 (L1) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0020, // Maximum Size + 0x0020, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction + CacheTypeData, // System Cache Type + CacheAssociativity4Way // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a73_L2 = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 3, // SocketDesignation String + 0x0181, // Cache Configuration + // Cache Level :3 (L2) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0800, // Maximum Size + 0x0800, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; + +SMBIOS_TABLE_TYPE7 mCacheInfoType7_a53_L2 = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 3, // SocketDesignation String + 0x0181, // Cache Configuration + // Cache Level :3 (L2) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0800, // Maximum Size + 0x0800, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 1, // Unknown :1 + 0, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; + +/*********************************************************************** + SMBIOS data definition TYPE17 Memory Device Information +************************************************************************/ +SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { + {EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof(SMBIOS_TABLE_TYPE17), 0}, + 0, // MemoryArrayHandle; // Should match SMBIOS_TABLE_TYPE16.Handle, + // initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + 0xFFFE, // MemoryErrorInformationHandle; (not provided) + 64, // TotalWidth; (unknown) + 64, // DataWidth; (unknown) + 0x2000, // Size; // When bit 15 is 0: Size in MB + // When bit 15 is 1: Size in KB, and continues in ExtendedSize + // initialized at runtime, refer to + // PhyMemArrayInfoUpdateSmbiosType16() + MemoryFormFactorRowOfChips, // FormFactor; ///< The + // enumeration value from MEMORY_FORM_FACTOR. + 0, // DeviceSet; + 1, // DeviceLocator String + 2, // BankLocator String + MemoryTypeLpddr4, // MemoryType; ///< The enumeration + // value from MEMORY_DEVICE_TYPE. + { + // TypeDetail; + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 0, // FastPaged :1; + 0, // StaticColumn :1; + 0, // PseudoStatic :1; + 0, // Rambus :1; + 0, // Synchronous :1; + 0, // Cmos :1; + 0, // Edo :1; + 0, // WindowDram :1; + 0, // CacheDram :1; + 0, // Nonvolatile :1; + 0, // Registered :1; + 1, // Unbuffered :1; + 0, // Reserved1 :1; + }, + 2133, // Speed; (unknown) + 2, // Manufacturer String + 0, // SerialNumber String + 0, // AssetTag String + 0, // PartNumber String + 0, // Attributes; (unknown rank) + 0, // ExtendedSize; (since Size < 32GB-1) + 0, // ConfiguredMemoryClockSpeed; (unknown) + 0, // MinimumVoltage; (unknown) + 0, // MaximumVoltage; (unknown) + 0, // ConfiguredVoltage; (unknown) + MemoryTechnologyDram, // MemoryTechnology ///< The + // enumeration value from MEMORY_DEVICE_TECHNOLOGY + {{ + // MemoryOperatingModeCapability + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 1, // VolatileMemory :1; + 0, // ByteAccessiblePersistentMemory :1; + 0, // BlockAccessiblePersistentMemory :1; + 0 // Reserved :10; + }}, + 0, // FirwareVersion + 0, // ModuleManufacturerID (unknown) + 0, // ModuleProductID (unknown) + 0, // MemorySubsystemControllerManufacturerID (unknown) + 0, // MemorySubsystemControllerProductID (unknown) + 0, // NonVolatileSize + 0xFFFFFFFFFFFFFFFFULL, // VolatileSize // initialized at runtime, refer to + // PhyMemArrayInfoUpdateSmbiosType16() + 0, // CacheSize + 0, // LogicalSize (since MemoryType is not + // MemoryTypeLogicalNonVolatileDevice) + 0, // ExtendedSpeed, + 0 // ExtendedConfiguredMemorySpeed +}; +CHAR8 *mMemDevInfoType17Strings[] = {"Builtin", "BANK 0", NULL}; + +VOID RegisterSOCSmbiosInfo( + SMBIOS_LOG_SMBIOS_DATA LogSmbiosData, + EFI_SMBIOS_HANDLE Type16 +){ + EFI_SMBIOS_HANDLE SmbiosHandle; + // TYPE7 Cache Information + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a73_L1I, + mCacheInfoType7Strings, NULL); + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a53_L1I, + mCacheInfoType7Strings, NULL); + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a73_L1D, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a73.L1CacheHandle = (UINT16)SmbiosHandle; + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a53_L1D, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a53.L1CacheHandle = (UINT16)SmbiosHandle; + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a73_L2, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a73.L2CacheHandle = (UINT16)SmbiosHandle; + + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7_a53_L2, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_a53.L2CacheHandle = (UINT16)SmbiosHandle; + + // TYPE4 Processor Information + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_a73, + mProcessorInfoType4Strings, NULL); + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_a53, + mProcessorInfoType4Strings, NULL); + + // TYPE17 Memory Device Information + mMemDevInfoType17.MemoryArrayHandle = Type16; + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings, + NULL); +} diff --git a/Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf b/Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf new file mode 100644 index 000000000..ccb0dd8f9 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf @@ -0,0 +1,19 @@ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SOCSmbiosInfoLib + FILE_GUID = 11F9F33F-2C69-460B-9613-79B967F8EFA6 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SOCSmbiosInfoLib + +[Sources] + SOCSmbiosInfo.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm6375/sm6375.dec + diff --git a/Silicon/Qualcomm/sm6375/sm6375.dec b/Silicon/Qualcomm/sm6375/sm6375.dec new file mode 100644 index 000000000..b3e80df38 --- /dev/null +++ b/Silicon/Qualcomm/sm6375/sm6375.dec @@ -0,0 +1,15 @@ +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = sm6375Pkg + PACKAGE_GUID = 8f169043-4634-42b9-adab-5040f633596c + PACKAGE_VERSION = 1.0 + +[Includes] + Include + +[Guids] + gsm6375PkgTokenSpaceGuid = { 0x99a14446, 0xaad7, 0xe460, {0xb4, 0xe5, 0x1f, 0x79, 0xaa, 0xa4, 0x93, 0xfd } } + +[PcdsFixedAtBuild.common] + + diff --git a/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MADT.aml b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/APIC.aml similarity index 100% rename from Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MADT.aml rename to Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/APIC.aml diff --git a/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/CSRT.aml b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/CSRT.aml new file mode 100644 index 000000000..354500ce2 Binary files /dev/null and b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/CSRT.aml differ diff --git a/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACS.aml b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACS.aml new file mode 100644 index 000000000..1e0249676 Binary files /dev/null and b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/FACS.aml differ diff --git a/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MCFG.aml b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MCFG.aml new file mode 100644 index 000000000..bf8334b8d Binary files /dev/null and b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/MCFG.aml differ diff --git a/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/SPCR.aml b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/SPCR.aml new file mode 100644 index 000000000..89d386891 Binary files /dev/null and b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/SPCR.aml differ diff --git a/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/TPM2.aml b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/TPM2.aml new file mode 100644 index 000000000..f74d05dd5 Binary files /dev/null and b/Silicon/Qualcomm/sm7125/AcpiTables/BuiltIn/TPM2.aml differ diff --git a/Silicon/Qualcomm/sm7125/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Silicon/Qualcomm/sm7125/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c index ed70feafe..20798e610 100644 --- a/Silicon/Qualcomm/sm7125/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c +++ b/Silicon/Qualcomm/sm7125/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -4,60 +4,73 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { /* Name Address Length HobOption ResourceAttribute ArmAttributes ResourceType MemoryType */ - - /* DDR Regions */ - {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, /* Added */ - // Check: RFSLocateAndProtectSharedArea will get called + /* DDR Regions */ + {"HYP", 0x80000000, 0x00600000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, /* Added */ {"MPSS_EFS", 0x80600000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"AOP Image", 0x80800000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"AOP Image", 0x80800000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, /* Added */ {"AOP CMD DB", 0x80820000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, {"GPU PRR", 0x80840000, 0x00010000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 1", 0x80850000, 0x000AF000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - {"SEC APPs", 0x808FF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED}, - {"TZ", 0x80B00000, 0x01700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, - // secapp-region - {"TZApps", 0x82200000, 0x02200000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, - {"PIL_REGION", 0x84400000, 0x0F800000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 2", 0x93C00000, 0x08400000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x80850000, 0x000AF000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"TZApps", 0x808ff000, 0x00001000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED}, + {"QSEE", 0x80B00000, 0x03900000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"HLOS Entry1", 0x84400000, 0x01700000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"PIL Reserved", 0x85B00000, 0x0EB00000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"DXE Heap", 0x94600000, 0x04500000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"DBI Dump", 0x98B00000, 0x00D70000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"HLOS Entry2", 0x99870000, 0x01F90000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"Sched Heap", 0x9B800000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x9BC00000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, {"Display Reserved", 0x9C000000, 0x01800000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, - {"Runtime Data", 0x9D800000, 0x00080000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, - {"Runtime Code", 0x9D880000, 0x00080000, AddMem, SYS_MEM, SYS_MEM_CAP, RtCode, WRITE_BACK_XN}, - {"HLOS 3", 0x9D900000, 0x00700000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - // qseecom_mem - {"TGCM", 0x9E000000, 0x01400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - {"HLOS 4", 0x9F400000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - {"FV Region", 0x9F800000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x9D800000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"ADSP RPC", 0x9DC00000, 0x00800000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"TGCM", 0x9E400000, 0x01400000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"FV Region", 0x9F800000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x9FA00000, 0x00200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, {"UEFI FD", 0x9FC00000, 0x00300000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, {"SEC Heap", 0x9FF00000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, {"CPU Vectors", 0x9FF8C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, {"MMU PageTables", 0x9FF8D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, - {"UEFI Stack", 0x9FF90000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"USB UCSI Temp", 0x9FF90000, 0x00002000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0x9FF92000, 0x0001E000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"UEFI Stack", 0x9FFB0000, 0x00020000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RSRV1", 0x9FFD0000, 0x0000A000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"TPMControl", 0x9FFDA000, 0x00003000, AddMem, MEM_RES, WRITE_COMBINEABLE, RtData, UNCACHED_UNBUFFERED_XN}, + {"Reset Data", 0x9FFDD000, 0x00004000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, UNCACHED_UNBUFFERED_XN}, + {"RSRV3", 0x9FFE1000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Capsule Header", 0x9FFE2000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, UNCACHED_UNBUFFERED_XN}, + {"RSRV2", 0x9FFE3000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + + + /************************************************** + * * + * RamPartitionDXE will add MLVM regions Later. * + * 0xA0000000 to MEMORY_HOLE_START_ADDR * + * * + **************************************************/ +// {"Hypervisor", 0x85700000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, /* Added */ +// {"TZ", 0x86200000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, /* Added */ +// {"RAM Partition", 0x89B00000, 0x01C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +// {"RAM Partition", 0x9FF92000, 0x0001E000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - // Note: Runtime memory has to be on an alignment of 0x10000 - {"RSRV1", 0x9FFD0000, 0x0000A000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"TPMControl", 0x9FFDA000, 0x00003000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, - {"Reset Data", 0x9FFDD000, 0x00004000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"RSRV3", 0x9FFE1000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"Capsule Header", 0x9FFE2000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, - {"RSRV2", 0x9FFE3000, 0x00014000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"Log Buffer", 0x9FFF7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"Info Blk", 0x9FFFF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, +// {"Secure DSP", 0xA0000000, 0x01200000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +// {"Kernel", 0xA1200000, 0x08000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +// {"MLVM_APSS", 0xA9200000, 0x03A00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +// {"MLVM_1", 0xACC00000, 0x0FC00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + //6GB + // Memory hole: 0xBC800000 - 0xBFFFFFFF BC800000 + // Size: 0x33FFFFF /* RAM partition regions */ - {"Secure DSP", 0xA0000000, 0x01200000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, - {"DXE Heap", 0xA1200000, 0x1B700000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - /* Memory hole */ - /* 0xBC900000 - 0xBFFFFFFF */ - {"DBI Dump", 0xC0000000, 0x00F00000, NoHob, MMAP_IO, INITIALIZED, Reserv, UNCACHED_UNBUFFERED_XN}, - {"RAM Partition", 0xC0F00000, 0x0D100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, - {"RAM Partition", 0xD0000000, 0xB0000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x0C0000000, 0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x100000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + /* Only need to map 4GB */ - {"RAM Partition", 0x180000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - {"RAM Partition", 0x1a0000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - {"RAM Partition", 0x1c0000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, - {"RAM Partition", 0x1e0000000, 0x20000000, Mem6G, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, +// {"RAM Partition", 0x180000000, 0x80000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, /* Other memory regions */ {"AOP_SS_MSG_RAM", 0x0C300000, 0x00100000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, @@ -65,7 +78,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { {"IMEM Cookie Base", 0x146AA000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, /* Register regions */ - {"GCC_CLK_CTL", 0x00100000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"GCC CLK CTL", 0x00100000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"PRNG_CFG_PRNG", 0x00790000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"SDC1_REG", 0x007C0000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, @@ -74,7 +87,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { {"UFS UFS REGS", 0x01D80000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"TCSR_TCSR_REGS", 0x01FC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - {"TLMM_EAST", 0x03500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x03500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"TLMM_NORTH", 0x03900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"TLMM_SOUTH", 0x03D00000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"GPU_CC", 0x05090000, 0x00009000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, @@ -89,6 +102,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { {"PDC_DISP_SEQ", 0x0B4A0000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"RPMH_BCM_BCM_TOP", 0x0BA00000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"SLP_CNTR_TSENS", 0x0C221000, 0x00003000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TSENS0_TM_PSHOLD", 0x0C263000, 0x00003000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"PMIC ARB SPMI", 0x0C400000, 0x02800000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"VIDEO_CC", 0x0AB00000, 0x00020000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"NPU_CC", 0x09980000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, @@ -100,7 +114,7 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { {"APSS_RSC_RSCCR", 0x18200000, 0x00030000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"APSS_GIC500_GICD", 0x17A00000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"APSS_GIC500_GICR", 0x17A60000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, - {"QTIMER", 0x17C00000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QTIMER", 0x17C20000, 0x00110000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"APSS_ACTPM_WRAP", 0x18300000, 0x000B0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"MDSS", 0x0AE00000, 0x00134000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, {"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, @@ -111,4 +125,4 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() { return gDeviceMemoryDescriptorEx; -} \ No newline at end of file +} diff --git a/Silicon/Qualcomm/sm8150/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c b/Silicon/Qualcomm/sm8150/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c index a7fc5516a..c0f60304d 100644 --- a/Silicon/Qualcomm/sm8150/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c +++ b/Silicon/Qualcomm/sm8150/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c @@ -165,7 +165,10 @@ PlatformUpdateAcpiTables(VOID) UpdateNameAslCode(SIGNATURE_32('S', 'U', 'S', '3'), &SUS3, 4); UpdateNameAslCode(SIGNATURE_32('S', 'I', 'D', 'T'), &SIDT, 4); UpdateNameAslCode(SIGNATURE_32('S', 'O', 'S', 'N'), &SOSN, 8); +#ifdef PLST_FIX + #else UpdateNameAslCode(SIGNATURE_32('P', 'L', 'S', 'T'), &PLST, 4); +#endif UpdateNameAslCode(SIGNATURE_32('R', 'M', 'T', 'B'), &RMTB, 4); UpdateNameAslCode(SIGNATURE_32('R', 'M', 'T', 'X'), &RMTX, 4); UpdateNameAslCode(SIGNATURE_32('R', 'F', 'M', 'B'), &RFMB, 4); diff --git a/Silicon/Qualcomm/sm8150/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Silicon/Qualcomm/sm8150/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c index d872ec4c0..700007ef9 100644 --- a/Silicon/Qualcomm/sm8150/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c +++ b/Silicon/Qualcomm/sm8150/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -197,4 +197,4 @@ static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() { return gDeviceMemoryDescriptorEx; -} \ No newline at end of file +} diff --git a/Silicon/Qualcomm/sm8475/Include/Configuration/DeviceConfigurationMap.h b/Silicon/Qualcomm/sm8475/Include/Configuration/DeviceConfigurationMap.h new file mode 100644 index 000000000..d95e42274 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Include/Configuration/DeviceConfigurationMap.h @@ -0,0 +1,56 @@ +#ifndef _DEVICE_CONFIGURATION_MAP_H_ +#define _DEVICE_CONFIGURATION_MAP_H_ + +#define CONFIGURATION_NAME_MAX_LENGTH 64 + +typedef struct { + CHAR8 Name[CONFIGURATION_NAME_MAX_LENGTH]; + UINT64 Value; +} CONFIGURATION_DESCRIPTOR_EX, *PCONFIGURATION_DESCRIPTOR_EX; + +static CONFIGURATION_DESCRIPTOR_EX gDeviceConfigurationDescriptorEx[] = { + {"AllowNonPersistentVarsInRetail", 0x1}, + {"APPS_HOB_ADDRESS", 0xE3400000}, + {"APPS_HOB_SIZE", 0x00001000}, + {"DDRInfoNotifyFlag", 0x0}, + {"DetectRetailUserAttentionHotkey", 0x00}, + {"DetectRetailUserAttentionHotkeyCode", 0x17}, + {"DloadCookieAddr", 0x01FD3000}, + {"DloadCookieValue", 0x10}, + {"EarlyInitCoreCnt", 2}, + {"EnableACPIFallback", 0x0}, + {"EnableDisplayImageFv", 0x0}, + {"EnableDisplayThread", 0x1}, + {"EnableLogFsSyncInRetail", 0x1}, + {"EnableMultiCoreFvDecompression", 1}, + {"EnableMultiThreading", 1}, + {"EnableOEMSetupAppInRetail", 0x0}, + {"EnableSDHCSwitch", 0x1}, + {"EnableShell", 0x1}, + {"EnableUefiSecAppDebugLogDump", 0x0}, + {"EnableUfsIOC", 1}, + {"EnableVariablePolicyEngine", 0}, + {"EUDEnableAddr", 0x88E2000}, + {"InitialPagePoolCount", 0x900}, + {"MaxCoreCnt", 8}, + {"MaxLogFileSize", 0x400000}, + {"MinidumpTALoadingCfg", 0x0}, + {"NumActiveCores", 8}, + {"NumCpus", 8}, + {"PwrBtnShutdownFlag", 0x0}, + {"Sdc1GpioConfigOff", 0xA00}, + {"Sdc1GpioConfigOn", 0x1E92}, + {"Sdc2GpioConfigOff", 0xA00}, + {"Sdc2GpioConfigOn", 0x1E92}, + {"SecurityFlag", 0x1C4}, + {"SharedIMEMBaseAddr", 0x146BF000}, + {"ShmBridgememSize", 0xA00000}, + {"SmcInvokeConfig", 0x20040100}, + {"UefiMemUseThreshold", 0xE1}, + {"UfsSmmuConfigForOtherBootDev", 1}, + {"UsbFnIoRevNum", 0x00010001}, + {"USBHS1_Config", 0x0}, + /* Terminator */ + {"Terminator", 0xFFFFFFFF}}; + +#endif diff --git a/Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c b/Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c new file mode 100644 index 000000000..4fc24b465 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.c @@ -0,0 +1,39 @@ +/** @file + *MsPlatformDevicesLib - Device specific library. +Copyright (C) Microsoft Corporation. All rights reserved. +SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +// #include +#include + +#include + +#include +#include +#include + +VOID +EFIAPI +PlatformSetup() +{ + // Allow MPSS and HLOS to access the allocated RFS Shared Memory Region + // Normally this would be done by a driver in Linux + // TODO: Move to a better place! + // RFSLocateAndProtectSharedArea(); + + // Patch ACPI Tables + // PlatformUpdateAcpiTables(); +} diff --git a/Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf b/Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf new file mode 100644 index 000000000..ad698ba14 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/MsPlatformDevicesLib/MsPlatformDevicesLib.inf @@ -0,0 +1,47 @@ +## @file +# Ms Platform Devices Library +# Ported from SurfaceDuoPkg +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (C) Microsoft Corporation. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = MsPlatformDevicesLib + FILE_GUID = 2FDF4E63-5AD5-4385-A729-868019B45A91 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = MsPlatformDevicesLib|DXE_DRIVER DXE_RUNTIME_DRIVER UEFI_APPLICATION + +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + MsPlatformDevicesLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RenegadePkg/RenegadePkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm8475/sm8475.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + DevicePathLib + IoLib + UefiBootServicesTableLib + UefiLib + # AslUpdateLib + # RFSProtectionLib + MemoryMapHelperLib + +[Protocols] + gEfiChipInfoProtocolGuid ## CONSUMES + gQcomSMEMProtocolGuid ## CONSUMES + gEfiPlatformInfoProtocolGuid ## CONSUMES diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c b/Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c new file mode 100644 index 000000000..3bddb5a00 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.c @@ -0,0 +1,105 @@ +#include +#include + +static ARM_MEMORY_REGION_DESCRIPTOR_EX gDeviceMemoryDescriptorEx[] = { + /* Name Address Length HobOption ResourceAttribute ArmAttributes + ResourceType MemoryType */ + + /* DDR Regions */ + /* DDR Bank 0 Start */ + {"Hypervisor", 0x80000000, 0x00600000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"Axon DMA", 0x80600000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + {"RAM Partition", 0x80700000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"AOP", 0x80800000, 0x00060000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"AOP CMD DB", 0x80860000, 0x00020000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"GPU PRR", 0x80880000, 0x00010000, AddMem, MEM_RES, WRITE_COMBINEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"TPMControl", 0x80890000, 0x00010000, AddMem, MEM_RES, WRITE_COMBINEABLE, RtData, UNCACHED_UNBUFFERED_XN}, + {"USB HLOS Shared", 0x808A0000, 0x00010000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"XBL LOGS", 0x808B0000, 0x00010000, AddMem, SYS_MEM, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 1", 0x808C0000, 0x00030000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x808F0000, 0x00010000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"SMEM", 0x80900000, 0x00200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"CPUCP FW", 0x80B00000, 0x00100000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 2", 0x80C00000, 0x02F00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"LPASS_NPU", 0x83B00000, 0x00F00000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"ADSP RPC", 0x84A00000, 0x00800000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"PIL Reserved", 0x85200000, 0x09200000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"HLOS 3", 0x8E400000, 0x10C00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD2", 0x9F000000, 0x00500000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"SEC Heap", 0x9F500000, 0x0008C000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"CPU Vectors", 0x9F58C000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"MMU PageTables", 0x9F58D000, 0x00003000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"UEFI Stack", 0x9F590000, 0x00040000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"RAM Partition", 0x9F5D0000, 0x00027000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Log Buffer", 0x9F5F7000, 0x00008000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Info Blk", 0x9F5FF000, 0x00001000, AddMem, SYS_MEM, SYS_MEM_CAP, RtData, WRITE_BACK_XN}, + {"Sched Resv Bckup", 0x9F600000, 0x00500000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"Sched Heap", 0x9FB00000, 0x00400000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"FV Region", 0x9FF00000, 0x00100000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK_XN}, + {"DXE Heap", 0xA0000000, 0x0EB00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"HYP RESERVED", 0xAEB00000, 0x11500000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, WRITE_BACK_XN}, + /* DDR Bank 0 End (0xB9700000) */ + /* Carveout Region (0xB9700000 -> 0xB9D00000, size 0x00600000) */ + /* DDR Bank 1 0xB9D00000 -> 0xBBB00000 */ + /* Carveout Region (0xBBB00000 -> 0xC0000000, size 0x04500000) */ + /* DDR Bank 2 Start */ + {"RAM Partition", 0xC0000000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"TZApps", 0xC1800000, 0x03900000, NoHob, SYS_MEM, SYS_MEM_CAP, Reserv, NS_DEVICE}, + {"DBI Dump", 0xC5100000, 0x01100000, NoHob, MMAP_IO, INITIALIZED, Conv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0xC6200000, 0x07E00000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"UEFI FD", 0xCE000000, 0x02000000, AddMem, SYS_MEM, SYS_MEM_CAP, BsData, WRITE_BACK}, + {"RAM Partition", 0xD0000000, 0x08800000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Removed Mem", 0xD8800000, 0x01800000, AddMem, SYS_MEM, SYS_MEM_CAP, Reserv, UNCACHED_UNBUFFERED_XN}, + {"TZApps Reserved", 0xDA000000, 0x03900000, HobOnlyNoCacheSetting, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0xDD900000, 0x03700000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"Display Reserved", 0xE1000000, 0x02400000, AddMem, MEM_RES, SYS_MEM_CAP, Reserv, WRITE_THROUGH_XN}, + {"Apps Hob", 0xE3400000, 0x00001000, AddMem, MEM_RES, UNCACHEABLE, Reserv, UNCACHED_UNBUFFERED_XN}, + {"RAM Partition", 0xE3401000, 0x5CBFF000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + + /* RAM partition regions */ + {"RAM Partition", 0x140000000,0x40000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + {"RAM Partition", 0x180000000,0x100000000, AddMem, SYS_MEM, SYS_MEM_CAP, Conv, WRITE_BACK_XN}, + /* DDR Bank 2 End */ + + /* Other memory regions */ + {"IMEM Base", 0x14680000, 0x00040000, NoHob, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + {"IMEM Cookie Base", 0x146BF000, 0x00001000, AddDev, MMAP_IO, INITIALIZED, Conv, NS_DEVICE}, + + /* Register regions */ + {"IPC_ROUTER_TOP", 0x00400000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SECURITY CONTROL", 0x00780000, 0x00007000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"QUP", 0x00800000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PRNG_CFG_PRNG", 0x010D0000, 0x00010000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"CRYPTO0 CRYPTO", 0x01DC0000, 0x00040000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TCSR_TCSR_REGS", 0x01F00000, 0x00100000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PERIPH_SS", 0x08800000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB", 0x0A400000, 0x00C00000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"AOSS", 0x0B000000, 0x04000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_WEST", 0x0F100000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_SOUTH", 0x0F500000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"TLMM_NORTH", 0x0F900000, 0x00300000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"SMMU", 0x15000000, 0x000D0000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"USB4", 0x15600000, 0x00200000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"APSS_HM", 0x17000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE},//TODO:need fix + {"PCIE_0_AXI", 0x60000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_1_AXI", 0x40000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_2A_AXI", 0x3C000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_2B_AXI", 0x38000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_3A_AXI", 0x34000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_3B_AXI", 0x32000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_4_AXI", 0x30000000, 0x02000000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_0_AHB", 0x01C30000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_1_AHB", 0x01C28000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_2A_AHB", 0x01C20000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_2B_AHB", 0x01C18000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_3A_AHB", 0x01C10000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_3B_AHB", 0x01C08000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + {"PCIE_4_AHB", 0x01C00000, 0x00008000, AddDev, MMAP_IO, UNCACHEABLE, MmIO, NS_DEVICE}, + + /* Terminator for MMU */ + {"Terminator", 0, 0, 0, 0, 0, 0, 0}}; + +ARM_MEMORY_REGION_DESCRIPTOR_EX *GetPlatformMemoryMap() +{ + return gDeviceMemoryDescriptorEx; +} \ No newline at end of file diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf b/Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf new file mode 100644 index 000000000..a0c806f38 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformMemoryMapLib/PlatformMemoryMapLib.inf @@ -0,0 +1,27 @@ +## @file +# PlatformMemoryMapLib +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) Renegade Project. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +## +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformMemoryMapLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F01 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformMemoryMapLib + +[Sources] + PlatformMemoryMapLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + +[LibraryClasses] + BaseLib diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.c b/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.c new file mode 100644 index 000000000..1bba17554 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.c @@ -0,0 +1,188 @@ +/** @file + Copyright (c) 2011-2014, ARM Limited. All rights reserved. + Copyright (c) 2014, Linaro Limited. All rights reserved. + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include "PlatformPeiLibInternal.h" + +STATIC +EFI_STATUS +CfgGetMemInfoByName( + CHAR8 *RegionName, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions) +{ + return LocateMemoryMapAreaByName(RegionName, MemRegions); +} + +STATIC +EFI_STATUS +CfgGetMemInfoByAddress( + UINT64 RegionBaseAddress, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions) +{ + return LocateMemoryMapAreaByAddress(RegionBaseAddress, MemRegions); +} + +STATIC +EFI_STATUS +CfgGetCfgInfoString(CHAR8 *Key, CHAR8 *Value, UINTN *ValBuffSize) +{ + if (AsciiStriCmp(Key, "OsTypeString") == 0) { + AsciiStrCpyS(Value, *ValBuffSize, "LA"); + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +CfgGetCfgInfoVal(CHAR8 *Key, UINT32 *Value) +{ + PCONFIGURATION_DESCRIPTOR_EX ConfigurationDescriptorEx = + gDeviceConfigurationDescriptorEx; + + // Run through each configuration descriptor + while (ConfigurationDescriptorEx->Value != 0xFFFFFFFF) { + if (AsciiStriCmp(Key, ConfigurationDescriptorEx->Name) == 0) { + *Value = (UINT32)(ConfigurationDescriptorEx->Value & 0xFFFFFFFF); + return EFI_SUCCESS; + } + ConfigurationDescriptorEx++; + } + + return EFI_NOT_FOUND; +} + +STATIC +EFI_STATUS +CfgGetCfgInfoVal64(CHAR8 *Key, UINT64 *Value) +{ + PCONFIGURATION_DESCRIPTOR_EX ConfigurationDescriptorEx = + gDeviceConfigurationDescriptorEx; + + // Run through each configuration descriptor + while (ConfigurationDescriptorEx->Value != 0xFFFFFFFF) { + if (AsciiStriCmp(Key, ConfigurationDescriptorEx->Name) == 0) { + *Value = ConfigurationDescriptorEx->Value; + return EFI_SUCCESS; + } + ConfigurationDescriptorEx++; + } + + return EFI_NOT_FOUND; +} + +STATIC +UINTN +SFlush(VOID) { return EFI_SUCCESS; } + +STATIC +UINTN +SControl(IN UINTN Arg, IN UINTN Param) { return EFI_SUCCESS; } + +STATIC +BOOLEAN +SPoll(VOID) { return TRUE; } + +STATIC +UINTN +SDrain(VOID) { return EFI_SUCCESS; } + +STATIC +EFI_STATUS +ShInstallLib(IN CHAR8 *LibName, IN UINT32 LibVersion, IN VOID *LibIntf) +{ + return EFI_SUCCESS; +} + +UefiCfgLibType ConfigLib = {0x00010002, CfgGetMemInfoByName, + CfgGetCfgInfoString, CfgGetCfgInfoVal, + CfgGetCfgInfoVal64, CfgGetMemInfoByAddress}; + +SioPortLibType SioLib = { + 0x00010001, SerialPortRead, SerialPortWrite, SPoll, + SDrain, SFlush, SControl, SerialPortSetAttributes, +}; + +STATIC +EFI_STATUS +ShLoadLib(CHAR8 *LibName, UINT32 LibVersion, VOID **LibIntf) +{ + if (LibIntf == NULL) + return EFI_NOT_FOUND; + + if (AsciiStriCmp(LibName, "UEFI Config Lib") == 0) { + *LibIntf = &ConfigLib; + return EFI_SUCCESS; + } + + if (AsciiStriCmp(LibName, "SerialPort Lib") == 0) { + *LibIntf = &SioLib; + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +ShLibLoaderType ShLib = {0x00010001, ShInstallLib, ShLoadLib}; + +STATIC +VOID BuildMemHobForFv(IN UINT16 Type) +{ + EFI_PEI_HOB_POINTERS HobPtr; + EFI_HOB_FIRMWARE_VOLUME2 *Hob = NULL; + + HobPtr.Raw = GetHobList(); + while ((HobPtr.Raw = GetNextHob(Type, HobPtr.Raw)) != NULL) { + if (Type == EFI_HOB_TYPE_FV2) { + Hob = HobPtr.FirmwareVolume2; + /* Build memory allocation HOB to mark it as BootServicesData */ + BuildMemoryAllocationHob( + Hob->BaseAddress, EFI_SIZE_TO_PAGES(Hob->Length) * EFI_PAGE_SIZE, + EfiBootServicesData); + } + HobPtr.Raw = GET_NEXT_HOB(HobPtr); + } +} + +STATIC GUID gEfiShLibHobGuid = EFI_SHIM_LIBRARY_GUID; +STATIC GUID gEfiInfoBlkHobGuid = EFI_INFORMATION_BLOCK_GUID; +STATIC GUID gFvDecompressHobGuid = EFI_FV_DECOMPRESS_GUID; + +VOID InstallPlatformHob() +{ + static int initialized = 0; + + if (!initialized) { + UINTN Data = (UINTN)&ShLib; + UINTN Data2 = 0x9FFFF000; + UINTN Data3 = 0x9FC403D0; + + BuildMemHobForFv(EFI_HOB_TYPE_FV2); + BuildGuidDataHob(&gEfiShLibHobGuid, &Data, sizeof(Data)); + BuildGuidDataHob(&gEfiInfoBlkHobGuid, &Data2, sizeof(Data2)); + BuildGuidDataHob(&gFvDecompressHobGuid, &Data3, sizeof(Data3)); + + initialized = 1; + } +} + +EFI_STATUS +EFIAPI +PlatformPeim( + VOID + ) +{ + + BuildFvHob(PcdGet64(PcdFvBaseAddress), PcdGet32(PcdFvSize)); + + InstallPlatformHob(); + + return EFI_SUCCESS; +} diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.inf b/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.inf new file mode 100644 index 000000000..23a48fbaa --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLib.inf @@ -0,0 +1,50 @@ +#/** @file +# +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPeiLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F06 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPeiLib + +[Sources] + PlatformPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm8475/sm8475.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + SerialPortLib + MemoryMapHelperLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvSize + +[Pcd] + gArmTokenSpaceGuid.PcdFvBaseAddress + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid + +[Guids] + gQcomProdmodeInfoGuid \ No newline at end of file diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLibInternal.h b/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLibInternal.h new file mode 100644 index 000000000..ff7c5af88 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformPeiLib/PlatformPeiLibInternal.h @@ -0,0 +1,95 @@ +#ifndef __PLATFORM_HOB_INTERNAL_H +#define __PLATFORM_HOB_INTERNAL_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// This varies by device +#include + +typedef EFI_STATUS (*GET_CONFIG_STRING)( + CHAR8 *Key, CHAR8 *Value, UINTN *ValBuffSize); +typedef EFI_STATUS (*GET_CONFIG_VAL)(CHAR8 *Key, UINT32 *Value); +typedef EFI_STATUS (*GET_CONFIG_VAL64)(CHAR8 *Key, UINT64 *Value); + +typedef EFI_STATUS (*GET_MEM_INFO_BY_NAME)( + CHAR8 *RegionName, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions); + +typedef EFI_STATUS (*GET_MEM_INFO_BY_ADDRESS)( + UINT64 RegionBaseAddress, ARM_MEMORY_REGION_DESCRIPTOR_EX *MemRegions); + +typedef struct { + UINT32 LibVersion; + GET_MEM_INFO_BY_NAME GetMemInfoByName; + GET_CONFIG_STRING GetCfgInfoString; + GET_CONFIG_VAL GetCfgInfoVal; + GET_CONFIG_VAL64 GetCfgInfoVal64; + GET_MEM_INFO_BY_ADDRESS GetMemInfoByAddress; +} UefiCfgLibType; + +typedef UINTN (*SIO_READ)(OUT UINT8 *Buffer, IN UINTN NumberOfBytes); +typedef UINTN (*SIO_WRITE)(IN UINT8 *Buffer, IN UINTN NumberOfBytes); +typedef BOOLEAN (*SIO_POLL)(VOID); +typedef UINTN (*SIO_DRAIN)(VOID); +typedef UINTN (*SIO_FLUSH)(VOID); +typedef UINTN (*SIO_CONTROL)(IN UINTN Arg, IN UINTN Param); +typedef EFI_STATUS (*SIO_SETATTRIBUTES)( + IN OUT UINT64 *BaudRate, IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, IN OUT EFI_STOP_BITS_TYPE *StopBits); + +typedef struct { + UINT32 LibVersion; + SIO_READ Read; + SIO_WRITE Write; + SIO_POLL Poll; + SIO_DRAIN Drain; + SIO_FLUSH Flush; + SIO_CONTROL Control; + SIO_SETATTRIBUTES SetAttributes; +} SioPortLibType; + +typedef EFI_STATUS (*INSTALL_LIB)( + IN CHAR8 *LibName, IN UINT32 LibVersion, IN VOID *LibIntf); + +typedef EFI_STATUS (*LOAD_LIB)( + IN CHAR8 *LibName, IN UINT32 LibVersion, OUT VOID **LibIntfPtr); + +typedef struct { + UINT32 LoaderVersion; + INSTALL_LIB InstallLib; + LOAD_LIB LoadLib; +} ShLibLoaderType; + +#define EFI_SHIM_LIBRARY_GUID \ + { \ + 0xbedaeabc, 0x5e70, 0x4d66, \ + { \ + 0x97, 0x33, 0x21, 0x3d, 0x07, 0x2b, 0x9d, 0x04 \ + } \ + } + +#define EFI_INFORMATION_BLOCK_GUID \ + { \ + 0x90a49afd, 0x422f, 0x08ae, \ + { \ + 0x96, 0x11, 0xe7, 0x88, 0xd3, 0x80, 0x48, 0x45 \ + } \ + } + +#define EFI_FV_DECOMPRESS_GUID \ + { \ + 0x12dbd93d, 0x402a, 0x416e, \ + { \ + 0xec, 0x20, 0x5f, 0x80, 0xcf, 0x5f, 0x7f, 0xe7 \ + } \ + } + +#endif // __PLATFORM_HOB_INTERNAL_H \ No newline at end of file diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformPrePiLib.inf b/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformPrePiLib.inf new file mode 100644 index 000000000..0c23e5a91 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformPrePiLib.inf @@ -0,0 +1,66 @@ +#/** @file +# +# Copyright (c) DuoWoA authors. All rights reserved. +# Copyright (c) 2011-2015, ARM Limited. All rights reserved. +# Copyright (c) 2014, Linaro Limited. All rights reserved. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = PlatformPrePiLib + FILE_GUID = 59C11815-F8DA-4F49-B4FB-EC1E41ED1F07 + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + LIBRARY_CLASS = PlatformPrePiLib + +[Sources] + PlatformUtils.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm8475/sm8475.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseLib + DebugLib + IoLib + ExtractGuidedSectionLib + LzmaDecompressLib + PeCoffGetEntryPointLib + PrePiHobListPointerLib + CacheMaintenanceLib + DebugAgentLib + SerialPortLib + MemoryAllocationLib + PrePiMemoryAllocationLib + PerformanceLib + HobLib + CompilerIntrinsicsLib + # Platform-specific libraries + MemoryInitPeiLib + PlatformPeiLib + PlatformPrePiLib + TimerLib + PrintLib + MemoryMapHelperLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString + +[FixedPcd] + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gQcomTokenSpaceGuid.PcdMipiFrameBufferAddress + gQcomTokenSpaceGuid.PcdMipiFrameBufferWidth + gQcomTokenSpaceGuid.PcdMipiFrameBufferHeight + gQcomTokenSpaceGuid.PcdMipiFrameBufferPixelBpp + gQcomTokenSpaceGuid.PcdHallSensorPin + gQcomTokenSpaceGuid.PcdHallSensorActiveLow \ No newline at end of file diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformUtils.c b/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformUtils.c new file mode 100644 index 000000000..a86eb2adb --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformUtils.c @@ -0,0 +1,47 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PlatformUtils.h" + +VOID InitializeSharedUartBuffers(VOID) +{ + INTN *pFbConPosition = + (INTN + *)(FixedPcdGet32(PcdMipiFrameBufferAddress) + (FixedPcdGet32(PcdMipiFrameBufferWidth) * FixedPcdGet32(PcdMipiFrameBufferHeight) * FixedPcdGet32(PcdMipiFrameBufferPixelBpp) / 8)); + + *(pFbConPosition + 0) = 0; + *(pFbConPosition + 1) = 0; +} + +VOID UartInit(VOID) +{ + SerialPortInitialize(); + InitializeSharedUartBuffers(); + + DEBUG((EFI_D_INFO, "\nRenegade Project edk2-msm (AArch64)\n")); + DEBUG( + (EFI_D_INFO, "Firmware version %s built %a %a\n\n", + (CHAR16 *)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__)); +} + +VOID PlatformInitialize(VOID) +{ + // Initialize UART Serial + UartInit(); + + // Initialize GIC + MmioWrite32( + GICR_WAKER_CURRENT_CPU, + (MmioRead32(GICR_WAKER_CURRENT_CPU) & ~GIC_WAKER_PROCESSORSLEEP)); +} diff --git a/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformUtils.h b/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformUtils.h new file mode 100644 index 000000000..d5c8bca4a --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/PlatformPrePiLib/PlatformUtils.h @@ -0,0 +1,14 @@ +#ifndef _PLATFORM_UTILS_H_ +#define _PLATFORM_UTILS_H_ + +#include + +#define GICR_WAKER 0x0014 +#define GICR_SIZE 0x20000 +#define GICR_WAKER_CURRENT_CPU FixedPcdGet64(PcdGicRedistributorsBase) + GICR_WAKER + +#define GIC_WAKER_PROCESSORSLEEP 2 + +VOID PlatformInitialize(VOID); + +#endif /* _PLATFORM_UTILS_H_ */ diff --git a/Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c b/Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c new file mode 100644 index 000000000..1d9ec6c10 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfo.c @@ -0,0 +1,337 @@ +#include +#include +#include +#include +#include + +/** + * 缓存和内存部分未完成. +*/ + +/*********************************************************************** + SMBIOS data definition TYPE4 Processor Information +************************************************************************/ +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_x2 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 3200, // MaxSpeed; + 3200, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 7, // PartNumber; + 1, // CoreCount; + 1, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_a710 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 2800, // MaxSpeed; + 2800, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 6, // PartNumber; + 3, // CoreCount; + 3, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +SMBIOS_TABLE_TYPE4 mProcessorInfoType4_a510 = { + {EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof(SMBIOS_TABLE_TYPE4), 0}, + 1, // Socket String + CentralProcessor, // ProcessorType; ///< The enumeration value from + // PROCESSOR_TYPE_DATA. + ProcessorFamilyIndicatorFamily2, // ProcessorFamily; ///< The + // enumeration value from + // PROCESSOR_FAMILY2_DATA. + 2, // ProcessorManufacture String; + { // ProcessorId; + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}}, + 3, // ProcessorVersion String; + { + // Voltage; + 0, // ProcessorVoltageCapability5V :1; + 0, // ProcessorVoltageCapability3_3V :1; + 0, // ProcessorVoltageCapability2_9V :1; + 0, // ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero. + 0, // ProcessorVoltageReserved :3; ///< Bits 4-6, must be + // zero. + 1 // ProcessorVoltageIndicateLegacy :1; + }, + 0, // ExternalClock; + 2000, // MaxSpeed; + 2000, // CurrentSpeed; + 0x41, // Status; + ProcessorUpgradeOther, // ProcessorUpgrade; ///< The enumeration + // value from PROCESSOR_UPGRADE. + 0, // L1CacheHandle; + 0, // L2CacheHandle; + 0xFFFF, // L3CacheHandle; + 0, // SerialNumber; + 0, // AssetTag; + 5, // PartNumber; + 4, // CoreCount; + 4, // EnabledCoreCount; + 0, // ThreadCount; + 0xEC, // ProcessorCharacteristics; ///< The enumeration value from + // PROCESSOR_CHARACTERISTIC_FLAGS ProcessorReserved1 :1; + // ProcessorUnknown :1; + // Processor64BitCapble :1; + // ProcessorMultiCore :1; + // ProcessorHardwareThread :1; + // ProcessorExecuteProtection :1; + // ProcessorEnhancedVirtualization :1; + // ProcessorPowerPerformanceCtrl :1; + // Processor128bitCapble :1; + // ProcessorReserved2 :7; + ProcessorFamilyARM, // ARM Processor Family; + 0, // CoreCount2; + 0, // EnabledCoreCount2; + 0, // ThreadCount2; +}; + +CHAR8 mCpuName[128] = "Qualcomm Snapdragon 8 Gen 1 plus"; + +CHAR8 *mProcessorInfoType4Strings[] = { + "BGA", "Qualcomm", "Snapdragon 8 Gen 1 plus", NULL}; + +/*********************************************************************** + SMBIOS data definition TYPE7 Cache Information +************************************************************************/ +SMBIOS_TABLE_TYPE7 mCacheInfoType7 = { + {EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof(SMBIOS_TABLE_TYPE7), 0}, + 3, // SocketDesignation String + 0x0181, // Cache Configuration + // Cache Level :3 (L2) + // Cache Socketed :1 (Not Socketed) + // Reserved :1 + // Location :2 (Internal) + // Enabled/Disabled :1 (Enabled) + // Operational Mode :2 (WB) + // Reserved :6 + 0x0400, // Maximum Size + 0x0400, // Install Size + { + // Supported SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + { + // Current SRAM Type + 0, // Other :1 + 0, // Unknown :1 + 1, // NonBurst :1 + 0, // Burst :1 + 0, // PiplelineBurst :1 + 0, // Synchronous :1 + 0, // Asynchronous :1 + 0 // Reserved :9 + }, + 0, // Cache Speed unknown + CacheErrorSingleBit, // Error Correction Multi + CacheTypeUnified, // System Cache Type + CacheAssociativity16Way // Associativity +}; +CHAR8 *mCacheInfoType7Strings[] = {"L1 Instruction", "L1 Data", "L2", NULL}; + +/*********************************************************************** + SMBIOS data definition TYPE17 Memory Device Information +************************************************************************/ +SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = { + {EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof(SMBIOS_TABLE_TYPE17), 0}, + 0, // MemoryArrayHandle; // Should match SMBIOS_TABLE_TYPE16.Handle, + // initialized at runtime, refer to PhyMemArrayInfoUpdateSmbiosType16() + 0xFFFE, // MemoryErrorInformationHandle; (not provided) + 64, // TotalWidth; (unknown) + 64, // DataWidth; (unknown) + 0x2000, // Size; // When bit 15 is 0: Size in MB + // When bit 15 is 1: Size in KB, and continues in ExtendedSize + // initialized at runtime, refer to + // PhyMemArrayInfoUpdateSmbiosType16() + MemoryFormFactorRowOfChips, // FormFactor; ///< The + // enumeration value from MEMORY_FORM_FACTOR. + 0, // DeviceSet; + 1, // DeviceLocator String + 2, // BankLocator String + MemoryTypeLpddr5, // MemoryType; ///< The enumeration + // value from MEMORY_DEVICE_TYPE. + { + // TypeDetail; + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 0, // FastPaged :1; + 0, // StaticColumn :1; + 0, // PseudoStatic :1; + 0, // Rambus :1; + 0, // Synchronous :1; + 0, // Cmos :1; + 0, // Edo :1; + 0, // WindowDram :1; + 0, // CacheDram :1; + 0, // Nonvolatile :1; + 0, // Registered :1; + 1, // Unbuffered :1; + 0, // Reserved1 :1; + }, + 4200, // Speed; (unknown) #TODO + 2, // Manufacturer String + 0, // SerialNumber String + 0, // AssetTag String + 0, // PartNumber String + 0, // Attributes; (unknown rank) + 0, // ExtendedSize; (since Size < 32GB-1) + 0, // ConfiguredMemoryClockSpeed; (unknown) + 0, // MinimumVoltage; (unknown) + 0, // MaximumVoltage; (unknown) + 0, // ConfiguredVoltage; (unknown) + MemoryTechnologyDram, // MemoryTechnology ///< The + // enumeration value from MEMORY_DEVICE_TECHNOLOGY + {{ + // MemoryOperatingModeCapability + 0, // Reserved :1; + 0, // Other :1; + 0, // Unknown :1; + 1, // VolatileMemory :1; + 0, // ByteAccessiblePersistentMemory :1; + 0, // BlockAccessiblePersistentMemory :1; + 0 // Reserved :10; + }}, + 0, // FirwareVersion + 0, // ModuleManufacturerID (unknown) + 0, // ModuleProductID (unknown) + 0, // MemorySubsystemControllerManufacturerID (unknown) + 0, // MemorySubsystemControllerProductID (unknown) + 0, // NonVolatileSize + 0xFFFFFFFFFFFFFFFFULL, // VolatileSize // initialized at runtime, refer to + // PhyMemArrayInfoUpdateSmbiosType16() + 0, // CacheSize + 0, // LogicalSize (since MemoryType is not + // MemoryTypeLogicalNonVolatileDevice) + 0, // ExtendedSpeed, + 0 // ExtendedConfiguredMemorySpeed +}; +CHAR8 *mMemDevInfoType17Strings[] = {"Builtin", "BANK 0", NULL}; + +VOID RegisterSOCSmbiosInfo( + SMBIOS_LOG_SMBIOS_DATA LogSmbiosData, + EFI_SMBIOS_HANDLE Type16 +){ + EFI_SMBIOS_HANDLE SmbiosHandle; + // TYPE7 Cache Information + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7, + mCacheInfoType7Strings, &SmbiosHandle); + mProcessorInfoType4_x2.L2CacheHandle = (UINT16)SmbiosHandle; + mProcessorInfoType4_a710.L2CacheHandle = (UINT16)SmbiosHandle; + mProcessorInfoType4_a510.L2CacheHandle = (UINT16)SmbiosHandle; + + // TYPE4 Processor Information + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_x2, + mProcessorInfoType4Strings, NULL); + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_a710, + mProcessorInfoType4Strings, NULL); + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4_a510, + mProcessorInfoType4Strings, NULL); + + // TYPE17 Memory Device Information + mMemDevInfoType17.MemoryArrayHandle = Type16; + LogSmbiosData( + (EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings, + NULL); +} diff --git a/Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf b/Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf new file mode 100644 index 000000000..718049e53 --- /dev/null +++ b/Silicon/Qualcomm/sm8475/Library/SOCSmbiosInfoLib/SOCSmbiosInfoLib.inf @@ -0,0 +1,18 @@ +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SOCSmbiosInfoLib + FILE_GUID = 11F9F33F-2C69-460B-9613-79B967F8EFA6 + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + LIBRARY_CLASS = SOCSmbiosInfoLib + +[Sources] + SOCSmbiosInfo.c + +[Packages] + ArmPkg/ArmPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + EmbeddedPkg/EmbeddedPkg.dec + Silicon/Qualcomm/QcomPkg/QcomPkg.dec + Silicon/Qualcomm/sm8475/sm8475.dec diff --git a/Silicon/Qualcomm/sm8475/sm8475.dec b/Silicon/Qualcomm/sm8475/sm8475.dec new file mode 100644 index 000000000..ecb770dcc --- /dev/null +++ b/Silicon/Qualcomm/sm8475/sm8475.dec @@ -0,0 +1,12 @@ +[Defines] + DEC_SPECIFICATION = 0x0001001A + PACKAGE_NAME = sm8475pkg + PACKAGE_GUID = 7ab7c460-b76b-17b3-7dfc-870ecba00d7a + PACKAGE_VERSION = 1.0 +[Includes] + Include + +[Guids] + gsm8475PkgTokenSpaceGuid = { 0x99a14446, 0xaad7, 0xe460, {0xb4, 0xe5, 0x1f, 0x79, 0xaa, 0xa4, 0x93, 0xfd } } + +[PcdsFixedAtBuild.common] diff --git a/Silicon/platform.sh.inc b/Silicon/platform.sh.inc index 5094016c5..aa2a44624 100644 --- a/Silicon/platform.sh.inc +++ b/Silicon/platform.sh.inc @@ -17,7 +17,7 @@ function platform_build_kernel(){ } function platform_build_bootimg(){ - python3 "${ROOTDIR}/tools/mkbootimg.py" \ + python3 "${ROOTDIR}/tools/mkbootimg.py" \ --kernel "${WORKSPACE}/uefi-${DEVICE}-kernel" \ --ramdisk ramdisk \ --kernel_offset 0x00000000 \ @@ -25,7 +25,7 @@ function platform_build_bootimg(){ --tags_offset 0x00000000 \ --os_version "${BOOTIMG_OS_VERSION}" \ --os_patch_level "${BOOTIMG_OS_PATCH_LEVEL}" \ - --header_version 1 \ + --header_version "${BOOTIMG_HEADER_VERSION}" \ -o "${OUTDIR}/boot-${DEVICE}${EXT}.img" \ ||return "$?" } diff --git a/configs/devices/a52q.conf b/configs/devices/a52q.conf index 9b3446705..b6c762069 100644 --- a/configs/devices/a52q.conf +++ b/configs/devices/a52q.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="a52q" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/a71.conf b/configs/devices/a71.conf new file mode 100644 index 000000000..b0c4656d6 --- /dev/null +++ b/configs/devices/a71.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM7150" +VENDOR_NAME="Samsung" +PLATFORM_NAME="a71" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-10" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/akershus.conf b/configs/devices/akershus.conf index 8c32c0c94..10f9dbb06 100644 --- a/configs/devices/akershus.conf +++ b/configs/devices/akershus.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="ZTE/akershus" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/alioth.conf b/configs/devices/alioth.conf index adfcff1fb..325e03921 100644 --- a/configs/devices/alioth.conf +++ b/configs/devices/alioth.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="alioth" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/apollo.conf b/configs/devices/apollo.conf index 1f4cbbafd..37e142c7d 100644 --- a/configs/devices/apollo.conf +++ b/configs/devices/apollo.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="apollo" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-05" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/atoll-qrd.conf b/configs/devices/atoll-qrd.conf index 792e40d9b..7d2126a7a 100644 --- a/configs/devices/atoll-qrd.conf +++ b/configs/devices/atoll-qrd.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="atoll-qrd" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/axolotl.conf b/configs/devices/axolotl.conf new file mode 100644 index 000000000..5a39f2499 --- /dev/null +++ b/configs/devices/axolotl.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SDM845" +VENDOR_NAME="SHIFT" +PLATFORM_NAME="axolotl" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-08" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/ayn-odin.conf b/configs/devices/ayn-odin.conf index 280eb9dca..f98f37280 100644 --- a/configs/devices/ayn-odin.conf +++ b/configs/devices/ayn-odin.conf @@ -4,4 +4,5 @@ PLATFORM_NAME="ayn-odin" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" -BOOTIMG_OS_VERSION=9.0.0 \ No newline at end of file +BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 \ No newline at end of file diff --git a/configs/devices/beryllium-ebbg.conf b/configs/devices/beryllium-ebbg.conf index 445d54280..75043ce6f 100644 --- a/configs/devices/beryllium-ebbg.conf +++ b/configs/devices/beryllium-ebbg.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="beryllium" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/beryllium-tianma.conf b/configs/devices/beryllium-tianma.conf index 445d54280..75043ce6f 100644 --- a/configs/devices/beryllium-tianma.conf +++ b/configs/devices/beryllium-tianma.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="beryllium" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/betalm.conf b/configs/devices/betalm.conf index 09d163721..9d69e3076 100644 --- a/configs/devices/betalm.conf +++ b/configs/devices/betalm.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="betalm" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/cepheus.conf b/configs/devices/cepheus.conf index 2989471f8..91ac52206 100644 --- a/configs/devices/cepheus.conf +++ b/configs/devices/cepheus.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="cepheus" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-05" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/cheeseburger.conf b/configs/devices/cheeseburger.conf index c96511de7..d9044b5f1 100644 --- a/configs/devices/cheeseburger.conf +++ b/configs/devices/cheeseburger.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="cheeseburger" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 # LineageOS 19 config # ACPI config diff --git a/configs/devices/clover.conf b/configs/devices/clover.conf index ab2e0d9e3..8489441ec 100644 --- a/configs/devices/clover.conf +++ b/configs/devices/clover.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="clover" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-12" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/dipper.conf b/configs/devices/dipper.conf index 30d211cfa..1e1adec12 100644 --- a/configs/devices/dipper.conf +++ b/configs/devices/dipper.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="dipper" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/dm1q.conf b/configs/devices/dm1q.conf new file mode 100644 index 000000000..9cce2165b --- /dev/null +++ b/configs/devices/dm1q.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8550" +VENDOR_NAME="Samsung" +PLATFORM_NAME="dm1q" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-12" +BOOTIMG_OS_VERSION=14.0.0 +BOOTIMG_HEADER_VERSION=4 diff --git a/configs/devices/draco.conf b/configs/devices/draco.conf index 5092bc5c8..42ef66bde 100644 --- a/configs/devices/draco.conf +++ b/configs/devices/draco.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="draco" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/dumpling.conf b/configs/devices/dumpling.conf index 79a339226..56b2e1328 100644 --- a/configs/devices/dumpling.conf +++ b/configs/devices/dumpling.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="dumpling" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 # LineageOS 19 config # ACPI config diff --git a/configs/devices/elish.conf b/configs/devices/elish.conf index b42e6c8c1..007750a27 100644 --- a/configs/devices/elish.conf +++ b/configs/devices/elish.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="elish" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-02" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/enchilada.conf b/configs/devices/enchilada.conf index 27d26c328..6e01d53d6 100644 --- a/configs/devices/enchilada.conf +++ b/configs/devices/enchilada.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="enchilada" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/equuleus.conf b/configs/devices/equuleus.conf index d7170688a..0bed66425 100644 --- a/configs/devices/equuleus.conf +++ b/configs/devices/equuleus.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="equuleus" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/fajita.conf b/configs/devices/fajita.conf index fe74b4e85..8183a9e60 100644 --- a/configs/devices/fajita.conf +++ b/configs/devices/fajita.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="fajita" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/flashlmdd.conf b/configs/devices/flashlmdd.conf new file mode 100755 index 000000000..a017a63f0 --- /dev/null +++ b/configs/devices/flashlmdd.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8150" +VENDOR_NAME="LG" +PLATFORM_NAME="flashlmdd" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-06" +BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/fog.conf b/configs/devices/fog.conf new file mode 100644 index 000000000..03d100dba --- /dev/null +++ b/configs/devices/fog.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM6225" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="fog" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-05" +BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/fuxi.conf b/configs/devices/fuxi.conf new file mode 100644 index 000000000..231ecac4c --- /dev/null +++ b/configs/devices/fuxi.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8550" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="fuxi" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-11" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/guacamole.conf b/configs/devices/guacamole.conf index 102184f1a..f673e7e9d 100644 --- a/configs/devices/guacamole.conf +++ b/configs/devices/guacamole.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="guacamole" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-6" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/guacamoleb.conf b/configs/devices/guacamoleb.conf index f1d265cb9..0d479cb74 100644 --- a/configs/devices/guacamoleb.conf +++ b/configs/devices/guacamoleb.conf @@ -3,5 +3,6 @@ VENDOR_NAME="Oneplus" PLATFORM_NAME="guacamoleb" # mkbootimg config -BOOTIMG_OS_PATCH_LEVEL="2022-12" -BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_OS_PATCH_LEVEL="2021-01" +BOOTIMG_OS_VERSION=10.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/h7000.conf b/configs/devices/h7000.conf index 08c42d8a7..0c82f94a2 100644 --- a/configs/devices/h7000.conf +++ b/configs/devices/h7000.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="h7000" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-12" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/hotdog.conf b/configs/devices/hotdog.conf index b38563fdb..d3eae286c 100755 --- a/configs/devices/hotdog.conf +++ b/configs/devices/hotdog.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="hotdog" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/hotdogb.conf b/configs/devices/hotdogb.conf new file mode 100755 index 000000000..c5a4c807b --- /dev/null +++ b/configs/devices/hotdogb.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8150" +VENDOR_NAME="Oneplus" +PLATFORM_NAME="hotdogb" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-08" +BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/instantnoodlep.conf b/configs/devices/instantnoodlep.conf index 3dafbfb6a..5d5b0e45c 100644 --- a/configs/devices/instantnoodlep.conf +++ b/configs/devices/instantnoodlep.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="instantnoodlep" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-05" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/j716f.conf b/configs/devices/j716f.conf index 50376107f..03740ec8d 100644 --- a/configs/devices/j716f.conf +++ b/configs/devices/j716f.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="j716f" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-04" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/joan.conf b/configs/devices/joan.conf index d713f8612..f9a517e63 100644 --- a/configs/devices/joan.conf +++ b/configs/devices/joan.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="joan" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/judyln.conf b/configs/devices/judyln.conf index 47412a900..ade4c22a4 100644 --- a/configs/devices/judyln.conf +++ b/configs/devices/judyln.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="judyln" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/judyp.conf b/configs/devices/judyp.conf index 2782b4c42..19617acda 100644 --- a/configs/devices/judyp.conf +++ b/configs/devices/judyp.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="judyp" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/judypn.conf b/configs/devices/judypn.conf index 7cdf1cd1c..a916b0682 100644 --- a/configs/devices/judypn.conf +++ b/configs/devices/judypn.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="judypn" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/lahaina-qrd.conf b/configs/devices/lahaina-qrd.conf index 31ecd6a3c..71df7bbcc 100644 --- a/configs/devices/lahaina-qrd.conf +++ b/configs/devices/lahaina-qrd.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="lahaina-qrd" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2021-10" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/linus.conf b/configs/devices/linus.conf index cf6311a76..7a0b4344b 100755 --- a/configs/devices/linus.conf +++ b/configs/devices/linus.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="linus" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-03" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/lisa.conf b/configs/devices/lisa.conf index 1ecd3b7fe..60162569e 100644 --- a/configs/devices/lisa.conf +++ b/configs/devices/lisa.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="lisa" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/lmi.conf b/configs/devices/lmi.conf new file mode 100644 index 000000000..8223c396a --- /dev/null +++ b/configs/devices/lmi.conf @@ -0,0 +1,12 @@ +SOC_PLATFORM="SM8250" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="lmi" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-08" +BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 + +# ACPI config +SPLIT_DSDT=true +USE_IASL=true diff --git a/configs/devices/m1882.conf b/configs/devices/m1882.conf index 2de4542ee..0ef1b06cd 100644 --- a/configs/devices/m1882.conf +++ b/configs/devices/m1882.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="m1882" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/m1892.conf b/configs/devices/m1892.conf index dd147a972..9503f362b 100644 --- a/configs/devices/m1892.conf +++ b/configs/devices/m1892.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="m1892" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # Tips： # Because there is no difference, the same configuration file has been used, or added separately later \ No newline at end of file diff --git a/configs/devices/mata.conf b/configs/devices/mata.conf index d5b338ba8..6960fffeb 100644 --- a/configs/devices/mata.conf +++ b/configs/devices/mata.conf @@ -5,4 +5,5 @@ PLATFORM_NAME="mata" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 # LineageOS 19 config diff --git a/configs/devices/mh2lm.conf b/configs/devices/mh2lm.conf index f2477e6df..073bcc1a0 100644 --- a/configs/devices/mh2lm.conf +++ b/configs/devices/mh2lm.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="mh2lm" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/mh2lm5g.conf b/configs/devices/mh2lm5g.conf new file mode 100644 index 000000000..883e4e06d --- /dev/null +++ b/configs/devices/mh2lm5g.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8150" +VENDOR_NAME="LG" +PLATFORM_NAME="mh2lm5g" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-06" +BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/miatoll.conf b/configs/devices/miatoll-huaxing.conf similarity index 85% rename from configs/devices/miatoll.conf rename to configs/devices/miatoll-huaxing.conf index e03ce08af..76cb47531 100644 --- a/configs/devices/miatoll.conf +++ b/configs/devices/miatoll-huaxing.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="miatoll" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/miatoll-tianma.conf b/configs/devices/miatoll-tianma.conf new file mode 100644 index 000000000..76cb47531 --- /dev/null +++ b/configs/devices/miatoll-tianma.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM7125" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="miatoll" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2022-06" +BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/mona.conf b/configs/devices/mona.conf index 2730d043f..725d87f76 100644 --- a/configs/devices/mona.conf +++ b/configs/devices/mona.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="mona" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/moonstone.conf b/configs/devices/moonstone.conf new file mode 100644 index 000000000..9eb1ce9d1 --- /dev/null +++ b/configs/devices/moonstone.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM6375" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="moonstone" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-05" +BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/nabu.conf b/configs/devices/nabu.conf index 324f96753..b1397655a 100644 --- a/configs/devices/nabu.conf +++ b/configs/devices/nabu.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="nabu" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-10" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/nitrogen.conf b/configs/devices/nitrogen.conf new file mode 100644 index 000000000..f47530ecb --- /dev/null +++ b/configs/devices/nitrogen.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SDM660" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="nitrogen" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-03" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/nx563j.conf b/configs/devices/nx563j.conf index 74ba2518c..cee1d953d 100644 --- a/configs/devices/nx563j.conf +++ b/configs/devices/nx563j.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="nx563j" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/nx606j.conf b/configs/devices/nx606j.conf index 2695ca699..2cdb2b43a 100644 --- a/configs/devices/nx606j.conf +++ b/configs/devices/nx606j.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="nx606j" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/nx616j.conf b/configs/devices/nx616j.conf index eb55ca273..c7d3fabdb 100644 --- a/configs/devices/nx616j.conf +++ b/configs/devices/nx616j.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="nx616j" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/nx619j.conf b/configs/devices/nx619j.conf index 070a1aefa..a6cbe8990 100644 --- a/configs/devices/nx619j.conf +++ b/configs/devices/nx619j.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="nx619j" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/nx729j.conf b/configs/devices/nx729j.conf index b5faa1f86..773529ce3 100644 --- a/configs/devices/nx729j.conf +++ b/configs/devices/nx729j.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="nx729j" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-11" BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/pafm00.conf b/configs/devices/pafm00.conf index c5a8ef1df..3eef29ed3 100644 --- a/configs/devices/pafm00.conf +++ b/configs/devices/pafm00.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="pafm00" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/pd1821.conf b/configs/devices/pd1821.conf index 05f5f5438..3d08e4605 100644 --- a/configs/devices/pd1821.conf +++ b/configs/devices/pd1821.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="vivo/pd1821" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/perseus.conf b/configs/devices/perseus.conf index 544a2f981..ceea2a53e 100644 --- a/configs/devices/perseus.conf +++ b/configs/devices/perseus.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="perseus" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/pipa.conf b/configs/devices/pipa.conf new file mode 100644 index 000000000..1f24c478f --- /dev/null +++ b/configs/devices/pipa.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8250" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="pipa" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-08" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/polaris.conf b/configs/devices/polaris.conf index 28bd92a0e..080ae4aa3 100644 --- a/configs/devices/polaris.conf +++ b/configs/devices/polaris.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="polaris" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 # ACPI config SPLIT_DSDT=true diff --git a/configs/devices/q2q.conf b/configs/devices/q2q.conf index 1b17ff34d..cd5bfd780 100644 --- a/configs/devices/q2q.conf +++ b/configs/devices/q2q.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="q2q" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-04" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/r11.conf b/configs/devices/r11.conf index 63c8ad4e6..75d12bdd5 100644 --- a/configs/devices/r11.conf +++ b/configs/devices/r11.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="r11" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-12" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/r11s.conf b/configs/devices/r11s.conf index d76306b8c..2f917506c 100644 --- a/configs/devices/r11s.conf +++ b/configs/devices/r11s.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="r11s" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-12" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/r5q.conf b/configs/devices/r5q.conf index 0eabce334..ae4a92c80 100644 --- a/configs/devices/r5q.conf +++ b/configs/devices/r5q.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="r5q" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-12" BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/r8q.conf b/configs/devices/r8q.conf index 7189005e0..2663192ab 100644 --- a/configs/devices/r8q.conf +++ b/configs/devices/r8q.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="r8q" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/sagit.conf b/configs/devices/sagit.conf index 2508df7f9..b99769252 100644 --- a/configs/devices/sagit.conf +++ b/configs/devices/sagit.conf @@ -5,4 +5,5 @@ PLATFORM_NAME="sagit" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-08" BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 # LineageOS 19 config diff --git a/configs/devices/sargo.conf b/configs/devices/sargo.conf index 7b7df7a3b..d918be56b 100644 --- a/configs/devices/sargo.conf +++ b/configs/devices/sargo.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="sargo" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/skr-a0.conf b/configs/devices/skr-a0.conf index a1a590f4e..653795a4e 100644 --- a/configs/devices/skr-a0.conf +++ b/configs/devices/skr-a0.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="skr-a0" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/spes.conf b/configs/devices/spes.conf new file mode 100644 index 000000000..d678fd397 --- /dev/null +++ b/configs/devices/spes.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM6225" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="spes" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-05" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/star2qltechn.conf b/configs/devices/star2qltechn.conf index 766966dbb..5cca35b90 100644 --- a/configs/devices/star2qltechn.conf +++ b/configs/devices/star2qltechn.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="star2qltechn" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/starqlte.conf b/configs/devices/starqlte.conf new file mode 100644 index 000000000..2d9b4a90b --- /dev/null +++ b/configs/devices/starqlte.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SDM845" +VENDOR_NAME="Samsung" +PLATFORM_NAME="starqlte" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2020-09" +BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/surya.conf b/configs/devices/surya.conf index 2b2d7cd08..ce9b67c20 100644 --- a/configs/devices/surya.conf +++ b/configs/devices/surya.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="surya" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-06" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/taimen.conf b/configs/devices/taimen.conf index f1aeacc17..8358df4e5 100644 --- a/configs/devices/taimen.conf +++ b/configs/devices/taimen.conf @@ -1,10 +1,11 @@ SOC_PLATFORM="MSM8998" -VENDOR_NAME="goole" +VENDOR_NAME="Google" PLATFORM_NAME="taimen" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-10" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # LineageOS 19 config # ACPI config diff --git a/configs/devices/tb-9707f.conf b/configs/devices/tb-9707f.conf new file mode 100644 index 000000000..eaa6ebf0a --- /dev/null +++ b/configs/devices/tb-9707f.conf @@ -0,0 +1,12 @@ +SOC_PLATFORM="SM8250" +VENDOR_NAME="Lenovo" +PLATFORM_NAME="tb-9707f" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-04" +BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 + +# ACPI config +SPLIT_DSDT=true +USE_IASL=true diff --git a/configs/devices/trident.conf b/configs/devices/trident.conf index 856ee0147..7eb2c8cb1 100644 --- a/configs/devices/trident.conf +++ b/configs/devices/trident.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="trident" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/vayu-huaxing.conf b/configs/devices/vayu-huaxing.conf index 254d0d9ad..7b8de4730 100755 --- a/configs/devices/vayu-huaxing.conf +++ b/configs/devices/vayu-huaxing.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="vayu" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-05" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/vayu-tianma.conf b/configs/devices/vayu-tianma.conf index 254d0d9ad..7b8de4730 100755 --- a/configs/devices/vayu-tianma.conf +++ b/configs/devices/vayu-tianma.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="vayu" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2022-05" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/walleye.conf b/configs/devices/walleye.conf index 7fbbd0f8c..488bb2fd6 100644 --- a/configs/devices/walleye.conf +++ b/configs/devices/walleye.conf @@ -5,6 +5,7 @@ PLATFORM_NAME="walleye" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-10" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 # LineageOS 19 config # ACPI config diff --git a/configs/devices/wayne.conf b/configs/devices/wayne.conf index eb97d79b9..d8ca13abf 100644 --- a/configs/devices/wayne.conf +++ b/configs/devices/wayne.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="wayne" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-12" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/whyred.conf b/configs/devices/whyred.conf index fdda47744..8c85eea73 100644 --- a/configs/devices/whyred.conf +++ b/configs/devices/whyred.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="whyred" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-12" BOOTIMG_OS_VERSION=11.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/winner.conf b/configs/devices/winner.conf new file mode 100644 index 000000000..14e0e841e --- /dev/null +++ b/configs/devices/winner.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8150" +VENDOR_NAME="Samsung" +PLATFORM_NAME="winner" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-08" +BOOTIMG_OS_VERSION=12.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/x00td.conf b/configs/devices/x00td.conf new file mode 100644 index 000000000..187267d59 --- /dev/null +++ b/configs/devices/x00td.conf @@ -0,0 +1,7 @@ +SOC_PLATFORM="SDM660" +VENDOR_NAME="Asus" +PLATFORM_NAME="x00td" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2023-03" +BOOTIMG_OS_VERSION=13.0.0 diff --git a/configs/devices/yudi.conf b/configs/devices/yudi.conf new file mode 100644 index 000000000..90d21fd70 --- /dev/null +++ b/configs/devices/yudi.conf @@ -0,0 +1,8 @@ +SOC_PLATFORM="SM8475" +VENDOR_NAME="Xiaomi" +PLATFORM_NAME="yudi" + +# mkbootimg config +BOOTIMG_OS_PATCH_LEVEL="2021-08" +BOOTIMG_OS_VERSION=13.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/devices/zs600kl.conf b/configs/devices/zs600kl.conf index d7ca2df7b..9c5d0fce6 100644 --- a/configs/devices/zs600kl.conf +++ b/configs/devices/zs600kl.conf @@ -5,3 +5,4 @@ PLATFORM_NAME="zs600kl" # mkbootimg config BOOTIMG_OS_PATCH_LEVEL="2020-09" BOOTIMG_OS_VERSION=9.0.0 +BOOTIMG_HEADER_VERSION=1 diff --git a/configs/sdm845.conf b/configs/sdm845.conf index a476a66a5..c6bd2dd53 100644 --- a/configs/sdm845.conf +++ b/configs/sdm845.conf @@ -1,2 +1,2 @@ FD_BASE=0xCE000000 -FD_SIZE=0x02000000 \ No newline at end of file +FD_SIZE=0x00700000 diff --git a/configs/sm6225.conf b/configs/sm6225.conf new file mode 100644 index 000000000..963f397ee --- /dev/null +++ b/configs/sm6225.conf @@ -0,0 +1,2 @@ +FD_BASE=0xCE000000 +FD_SIZE=0x00700000 \ No newline at end of file diff --git a/configs/sm6375.conf b/configs/sm6375.conf new file mode 100644 index 000000000..963f397ee --- /dev/null +++ b/configs/sm6375.conf @@ -0,0 +1,2 @@ +FD_BASE=0xCE000000 +FD_SIZE=0x00700000 \ No newline at end of file diff --git a/configs/sm7125.conf b/configs/sm7125.conf index a476a66a5..c6bd2dd53 100644 --- a/configs/sm7125.conf +++ b/configs/sm7125.conf @@ -1,2 +1,2 @@ FD_BASE=0xCE000000 -FD_SIZE=0x02000000 \ No newline at end of file +FD_SIZE=0x00700000 diff --git a/configs/sm8475.conf b/configs/sm8475.conf new file mode 100644 index 000000000..055cbec7a --- /dev/null +++ b/configs/sm8475.conf @@ -0,0 +1,2 @@ +FD_BASE=0xCE000000 +FD_SIZE=0x02000000 diff --git a/tools/Installer b/tools/Installer index e4cf11f2a..799687746 160000 --- a/tools/Installer +++ b/tools/Installer @@ -1 +1 @@ -Subproject commit e4cf11f2a5df92859e4d1ea244ad3aa44372864d +Subproject commit 79968774636af5ce259c66928716eacdc9c1b815