Deep LVS failing

[stafverhaegen-chipflow]

I have a teststructure that fails deep LVS but goes through flat LVS. This both for the LVS deck provided by IHP as for my Chips4Makers generated LVS deck. We both use extend("*") to get the full design (see also IHP-GmbH/IHP-Open-PDK#254).
I now made an extra test case where I used the global net connection as described in #1813: testcase_deep2.tar.gz. This also fails.
Problem seems to be that the nmoses are extracted at the wrong level in the hierarchy.
I am using klayout v0.29.8

[klayoutmatthias]

Ah, these lovely SRAM layouts ...

The problem is a known one and the (current) solution are "cheats": https://www.klayout.de/doc-qt5/about/drc_ref_global.html#k_17

Here is for example a discussion with a similar problem: https://www.klayout.de/forum/discussion/comment/11290#Comment_11290

In your case, the fix is:

# somewhere at the beginning of the LVS script:
sram_cells = [ "SP6TCCell" ]

...

# upon device extraction add the "cheat" bracket:
cheat(sram_cells) {

  # Transistors
  # sg13g2_hv_nmos
  extract_devices(mos4("sg13_hv_nmos"), {
      "SD" => Activ__conn, "G" => gate__mosfet__sg13g2_hv_nmos, "tG" => GatPoly__conn, "W" => substrate__IHPSG13G2,
  })
  # sg13g2_hv_pmos
  extract_devices(mos4("sg13_hv_pmos"), {
      "SD" => Activ__conn, "G" => gate__mosfet__sg13g2_hv_pmos, "tG" => GatPoly__conn, "W" => NWell,
  })
  # sg13g2_lv_nmos
  extract_devices(mos4("sg13_lv_nmos"), {
      "SD" => Activ__conn, "G" => gate__mosfet__sg13g2_lv_nmos, "tG" => GatPoly__conn, "W" => substrate__IHPSG13G2,
  })
  # sg13g2_lv_pmos
  extract_devices(mos4("sg13_lv_pmos"), {
      "SD" => Activ__conn, "G" => gate__mosfet__sg13g2_lv_pmos, "tG" => GatPoly__conn, "W" => NWell,
  })

}

With this modification, LVS passes in my case.

This problem happens frequently with cells sharing devices - specifically, when the drain and source areas of the devices stretch over multiple cells. In your case, this region is shared between the cells:

KLayout collects all shapes that form source or drain in order to properly derive the size of the device. But the full shape of source or drain only appears one level up in the hierarchy. Here, the difference is only in AD or AS, but basically a device could be split along the gate and extend over two cells. In that case, the width can only be measured in the full device which is not available in the subcell. As a consequence, devices appear one level up.

The "cheat" cheat pretends that for the listed cells there is no neighborhood to consider. So device extraction does not try to collect shapes from adjacent cells and the devices are formed in the subcell.

I agree that is not really nice, but I think, this usually applies to a limited subset of cells (SRAM, decoders, ...).

I have tried an improved implementation that compromises proper extraction of AD/AS in favor a better hierarchical extraction of the devices (branch "device-extraction-improvement"). I will use this problem as a test for this implementation. But I have not released that yet.

Best regards,

Matthias