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contador.csv
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# Copyright (C) 2021 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
# Quartus Prime Version 21.1.0 Build 842 10/21/2021 SJ Lite Edition
# File: D:\eltd11a\laboratorio_07\lab_07_04\contador.csv
# Generated on: Mon Mar 7 23:54:24 2022
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
a10,Output,PIN_C14,7,B7_N0,PIN_C14,3.3-V LVTTL,,,,,
a20,Output,PIN_C18,7,B7_N0,PIN_C18,3.3-V LVTTL,,,,,
b11,Output,PIN_E15,7,B7_N0,PIN_E15,3.3-V LVTTL,,,,,
b21,Output,PIN_D18,6,B6_N0,PIN_D18,3.3-V LVTTL,,,,,
c12,Output,PIN_C15,7,B7_N0,PIN_C15,3.3-V LVTTL,,,,,
c22,Output,PIN_E18,6,B6_N0,PIN_E18,3.3-V LVTTL,,,,,
CLKA,Input,PIN_B8,7,B7_N0,PIN_B8,3.3 V Schmitt Trigger,,,,,
d13,Output,PIN_C16,7,B7_N0,PIN_C16,3.3-V LVTTL,,,,,
d23,Output,PIN_B16,7,B7_N0,PIN_B16,3.3-V LVTTL,,,,,
e14,Output,PIN_E16,7,B7_N0,PIN_E16,3.3-V LVTTL,,,,,
e24,Output,PIN_A17,7,B7_N0,PIN_A17,3.3-V LVTTL,,,,,
f15,Output,PIN_D17,7,B7_N0,PIN_D17,3.3-V LVTTL,,,,,
f25,Output,PIN_A18,7,B7_N0,PIN_A18,3.3-V LVTTL,,,,,
g16,Output,PIN_C17,7,B7_N0,PIN_C17,3.3-V LVTTL,,,,,
g26,Output,PIN_B17,7,B7_N0,PIN_B17,3.3-V LVTTL,,,,,
QAD,Output,PIN_D13,7,B7_N0,PIN_D13,3.3-V LVTTL,,,,,
QAU,Output,PIN_A8,7,B7_N0,PIN_A8,3.3-V LVTTL,,,,,
QBD,Output,PIN_C13,7,B7_N0,PIN_C13,3.3-V LVTTL,,,,,
QBU,Output,PIN_A9,7,B7_N0,PIN_A9,3.3-V LVTTL,,,,,
QCD,Output,PIN_E14,7,B7_N0,PIN_E14,3.3-V LVTTL,,,,,
QCU,Output,PIN_A10,7,B7_N0,PIN_A10,3.3-V LVTTL,,,,,
QDD,Output,PIN_D14,7,B7_N0,PIN_D14,3.3-V LVTTL,,,,,
QDU,Output,PIN_B10,7,B7_N0,PIN_B10,3.3-V LVTTL,,,,,
Ro1_Ro2,Input,PIN_C10,7,B7_N0,PIN_C10,3.3-V LVTTL,,,,,