From 5312f662e8995747b22fe40466a22d1628b71330 Mon Sep 17 00:00:00 2001 From: Mazen Kharbutli Date: Fri, 1 Jun 2018 12:37:10 -0700 Subject: [PATCH] i#3037: Add support for inclusive caches in DRCacheSim. (#3036) Add support for inclusive caches and cache line invalidation in DRCacheSim. No support for setting the "inclusive" field and the "children" vector are included in this commit because a new configuration file-based interface to the simulator is being added in a subsequent commit. Tests for inclusive caches will be added in the subsequent commit. Fixes #3037 --- clients/drcachesim/simulator/cache.cpp | 6 ++-- clients/drcachesim/simulator/cache.h | 4 ++- clients/drcachesim/simulator/cache_fifo.cpp | 6 ++-- clients/drcachesim/simulator/cache_fifo.h | 3 +- .../drcachesim/simulator/caching_device.cpp | 34 ++++++++++++++++++- clients/drcachesim/simulator/caching_device.h | 14 +++++++- .../simulator/caching_device_stats.cpp | 13 +++++-- .../simulator/caching_device_stats.h | 5 +++ clients/drcachesim/tests/TLB-simple.templatex | 3 ++ .../drcachesim/tests/TLB-threads.templatex | 3 ++ .../tests/allasm-aarch64-cache.templatex | 3 ++ clients/drcachesim/tests/allasm-arm.templatex | 3 ++ .../drcachesim/tests/allasm-thumb.templatex | 3 ++ .../drcachesim/tests/delay-simple.templatex | 3 ++ .../drcachesim/tests/filter-no-d.templatex | 3 ++ .../drcachesim/tests/filter-no-i.templatex | 3 ++ .../drcachesim/tests/filter-simple.templatex | 3 ++ clients/drcachesim/tests/multiproc.templatex | 5 +++ .../tests/offline-burst_client.templatex | 3 ++ .../tests/offline-burst_maps.templatex | 3 ++ .../tests/offline-burst_noreach.templatex | 3 ++ .../tests/offline-burst_replace.templatex | 3 ++ .../tests/offline-burst_replaceall.templatex | 3 ++ .../tests/offline-burst_static.templatex | 3 ++ .../tests/offline-burst_threads.templatex | 7 ++-- .../drcachesim/tests/offline-filter.templatex | 3 ++ .../tests/offline-multiproc.templatex | 3 ++ .../drcachesim/tests/offline-simple.templatex | 3 ++ clients/drcachesim/tests/phys.templatex | 3 ++ clients/drcachesim/tests/simple.templatex | 3 ++ clients/drcachesim/tests/threads.templatex | 3 ++ .../drcachesim/tests/warmup-valid.templatex | 3 ++ .../drcachesim/tests/warmup-zeros.templatex | 3 ++ 33 files changed, 154 insertions(+), 12 deletions(-) diff --git a/clients/drcachesim/simulator/cache.cpp b/clients/drcachesim/simulator/cache.cpp index 9b5c4b4df55..b93c7c30011 100644 --- a/clients/drcachesim/simulator/cache.cpp +++ b/clients/drcachesim/simulator/cache.cpp @@ -37,13 +37,15 @@ bool cache_t::init(int associativity_, int line_size_, int total_size, caching_device_t *parent_, caching_device_stats_t *stats_, - prefetcher_t *prefetcher_) + prefetcher_t *prefetcher_, bool inclusive_, + const std::vector& children_) { // convert total_size to num_blocks to fit for caching_device_t::init int num_lines = total_size / line_size_; return caching_device_t::init(associativity_, line_size_, num_lines, - parent_, stats_, prefetcher_); + parent_, stats_, prefetcher_, inclusive_, + children_); } void diff --git a/clients/drcachesim/simulator/cache.h b/clients/drcachesim/simulator/cache.h index 17272d85edc..910acfe9ad6 100644 --- a/clients/drcachesim/simulator/cache.h +++ b/clients/drcachesim/simulator/cache.h @@ -47,7 +47,9 @@ class cache_t : public caching_device_t // to describe a CPU cache. virtual bool init(int associativity, int line_size, int total_size, caching_device_t *parent, caching_device_stats_t *stats, - prefetcher_t *prefetcher = nullptr); + prefetcher_t *prefetcher = nullptr, + bool inclusive = false, + const std::vector& children = {}); virtual void request(const memref_t &memref); virtual void flush(const memref_t &memref); protected: diff --git a/clients/drcachesim/simulator/cache_fifo.cpp b/clients/drcachesim/simulator/cache_fifo.cpp index 1bf6d3b8df1..190ed8a7ab7 100644 --- a/clients/drcachesim/simulator/cache_fifo.cpp +++ b/clients/drcachesim/simulator/cache_fifo.cpp @@ -41,13 +41,15 @@ bool cache_fifo_t::init(int associativity_, int block_size_, int total_size, caching_device_t *parent_, caching_device_stats_t *stats_, - prefetcher_t *prefetcher_) + prefetcher_t *prefetcher_, bool inclusive_, + const std::vector& children_) { // Works in the same way as the base class, // except that the counters are initialized in a different way. bool ret_val = cache_t::init(associativity_, block_size_, total_size, - parent_, stats_, prefetcher_); + parent_, stats_, prefetcher_, inclusive_, + children_); if (ret_val == false) return false; diff --git a/clients/drcachesim/simulator/cache_fifo.h b/clients/drcachesim/simulator/cache_fifo.h index e026b5c629e..d40b185dbcb 100644 --- a/clients/drcachesim/simulator/cache_fifo.h +++ b/clients/drcachesim/simulator/cache_fifo.h @@ -43,7 +43,8 @@ class cache_fifo_t : public cache_t public: virtual bool init(int associativity, int line_size, int total_size, caching_device_t *parent, caching_device_stats_t *stats, - prefetcher_t *prefetcher); + prefetcher_t *prefetcher, bool inclusive = false, + const std::vector& children = {}); protected: virtual void access_update(int line_idx, int way); diff --git a/clients/drcachesim/simulator/caching_device.cpp b/clients/drcachesim/simulator/caching_device.cpp index 22be284de3a..7fa7a531dd4 100644 --- a/clients/drcachesim/simulator/caching_device.cpp +++ b/clients/drcachesim/simulator/caching_device.cpp @@ -55,7 +55,8 @@ caching_device_t::~caching_device_t() bool caching_device_t::init(int associativity_, int block_size_, int num_blocks_, caching_device_t *parent_, caching_device_stats_t *stats_, - prefetcher_t *prefetcher_) + prefetcher_t *prefetcher_, bool inclusive_, + const std::vector& children_) { if (!IS_POWER_OF_2(associativity_) || !IS_POWER_OF_2(block_size_) || @@ -85,6 +86,10 @@ caching_device_t::init(int associativity_, int block_size_, int num_blocks_, init_blocks(); last_tag = TAG_INVALID; // sentinel + + inclusive = inclusive_; + children = children_; + return true; } @@ -147,6 +152,11 @@ caching_device_t::request(const memref_t &memref_in) // the block loaded count. if (get_caching_device_block(block_idx, way).tag == TAG_INVALID) { loaded_blocks++; + } else if (inclusive && !children.empty()) { + for (auto &child : children) { + child->invalidate( + get_caching_device_block(block_idx, way).tag); + } } get_caching_device_block(block_idx, way).tag = tag; } @@ -200,3 +210,25 @@ caching_device_t::replace_which_way(int block_idx) get_caching_device_block(block_idx, min_way).counter = 0; return min_way; } + +void +caching_device_t::invalidate(const addr_t tag) +{ + int block_idx = compute_block_idx(tag); + + for (int way = 0; way < associativity; ++way) { + auto &cache_block = get_caching_device_block(block_idx, way); + if (cache_block.tag == tag) { + cache_block.tag = TAG_INVALID; + cache_block.counter = 0; + stats->invalidate(); + // Invalidate the block in the children's caches. + if (inclusive && !children.empty()) { + for (auto &child : children) { + child->invalidate(tag); + } + } + break; + } + } +} diff --git a/clients/drcachesim/simulator/caching_device.h b/clients/drcachesim/simulator/caching_device.h index d423543ae01..0c84d2548bb 100644 --- a/clients/drcachesim/simulator/caching_device.h +++ b/clients/drcachesim/simulator/caching_device.h @@ -36,6 +36,8 @@ #ifndef _CACHING_DEVICE_H_ #define _CACHING_DEVICE_H_ 1 +#include + #include "caching_device_block.h" #include "caching_device_stats.h" #include "memref.h" @@ -55,9 +57,12 @@ class caching_device_t caching_device_t(); virtual bool init(int associativity, int block_size, int num_blocks, caching_device_t *parent, caching_device_stats_t *stats, - prefetcher_t *prefetcher = nullptr); + prefetcher_t *prefetcher = nullptr, + bool inclusive = false, + const std::vector& children = {}); virtual ~caching_device_t(); virtual void request(const memref_t &memref); + virtual void invalidate(const addr_t tag); caching_device_stats_t *get_stats() const { return stats; } void set_stats(caching_device_stats_t *stats_) { stats = stats_; } @@ -86,7 +91,14 @@ class caching_device_t int num_blocks; // Current valid blocks in the cache int loaded_blocks; + + // Pointers to the caching device's parent and children devices. caching_device_t *parent; + std::vector children; + + // If true, this device is inclusive of its children. + bool inclusive; + // This should be an array of caching_device_block_t pointers, otherwise // an extended block class which has its own member variables cannot be indexed // correctly by base class pointers. diff --git a/clients/drcachesim/simulator/caching_device_stats.cpp b/clients/drcachesim/simulator/caching_device_stats.cpp index 7b7ad8b4cff..c9c9679af6e 100644 --- a/clients/drcachesim/simulator/caching_device_stats.cpp +++ b/clients/drcachesim/simulator/caching_device_stats.cpp @@ -38,8 +38,8 @@ caching_device_stats_t::caching_device_stats_t(const std::string &miss_file, bool warmup_enabled) : success(true), num_hits(0), num_misses(0), num_child_hits(0), - num_hits_at_reset(0), num_misses_at_reset(0), num_child_hits_at_reset(0), - warmup_enabled(warmup_enabled), file(nullptr) + num_inclusive_invalidates(0), num_hits_at_reset(0), num_misses_at_reset(0), + num_child_hits_at_reset(0), warmup_enabled(warmup_enabled), file(nullptr) { if (miss_file.empty()) { dump_misses = false; @@ -126,6 +126,8 @@ caching_device_stats_t::print_counts(std::string prefix) std::setw(20) << std::right << num_hits << std::endl; std::cerr << prefix << std::setw(18) << std::left << "Misses:" << std::setw(20) << std::right << num_misses << std::endl; + std::cerr << prefix << std::setw(18) << std::left << "Invalidations:" << + std::setw(20) << std::right << num_inclusive_invalidates << std::endl; } void @@ -176,4 +178,11 @@ caching_device_stats_t::reset() num_hits = 0; num_misses = 0; num_child_hits = 0; + num_inclusive_invalidates = 0; +} + +void +caching_device_stats_t::invalidate() +{ + num_inclusive_invalidates++; } diff --git a/clients/drcachesim/simulator/caching_device_stats.h b/clients/drcachesim/simulator/caching_device_stats.h index 690ea401a28..bee80951089 100644 --- a/clients/drcachesim/simulator/caching_device_stats.h +++ b/clients/drcachesim/simulator/caching_device_stats.h @@ -64,6 +64,9 @@ class caching_device_stats_t virtual bool operator!() { return !success; } + // Process invalidations due to cache inclusions. + virtual void invalidate(); + protected: bool success; @@ -79,6 +82,8 @@ class caching_device_stats_t int_least64_t num_misses; int_least64_t num_child_hits; + int_least64_t num_inclusive_invalidates; + // Stats saved when the last reset was called. This helps us get insight // into what the stats were when the cache was warmed up. int_least64_t num_hits_at_reset; diff --git a/clients/drcachesim/tests/TLB-simple.templatex b/clients/drcachesim/tests/TLB-simple.templatex index 5d0cd33f4c5..5a39c91c55d 100644 --- a/clients/drcachesim/tests/TLB-simple.templatex +++ b/clients/drcachesim/tests/TLB-simple.templatex @@ -5,14 +5,17 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 Miss rate: *[0-9]*[,\.]..% LL stats: Hits: *[0-9,\.]* Misses: *[0-9]..? + Invalidations: *0 Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]* Total miss rate: 0[,\.]..% diff --git a/clients/drcachesim/tests/TLB-threads.templatex b/clients/drcachesim/tests/TLB-threads.templatex index d2660aaed1d..c379cc55f91 100644 --- a/clients/drcachesim/tests/TLB-threads.templatex +++ b/clients/drcachesim/tests/TLB-threads.templatex @@ -69,14 +69,17 @@ Core #0 \([0-9] traced CPU\(s\): [#0-9, ]+\) L1I stats: Hits: *[0-9]*[,\.]?...[,\.]?... Misses: *[0-9,\.]* + Invalidations: *0 Miss rate: [0-4][\.,]..% L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 Miss rate: *[0-9]*[\.,]..% LL stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 Local miss rate: *[0-9]*[\.,]..% Child hits: *[0-9,\.]* Total miss rate: [0-4][\.,]..% diff --git a/clients/drcachesim/tests/allasm-aarch64-cache.templatex b/clients/drcachesim/tests/allasm-aarch64-cache.templatex index ba5e7fefeea..c2e6efadb41 100644 --- a/clients/drcachesim/tests/allasm-aarch64-cache.templatex +++ b/clients/drcachesim/tests/allasm-aarch64-cache.templatex @@ -5,10 +5,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: * 8[,.]?246 Misses: 2 + Invalidations: * 0 Miss rate: 0[.,]02% L1D stats: Hits: * 2[,.]?030 Misses: 16 + Invalidations: * 0 Miss rate: 0[.,]78% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -16,6 +18,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: 0 Misses: 18 + Invalidations: * 0 Local miss rate: 100[.,]00% Child hits: * 10[,.]?276 Total miss rate: 0[.,]17% diff --git a/clients/drcachesim/tests/allasm-arm.templatex b/clients/drcachesim/tests/allasm-arm.templatex index 7baa6f2d783..7b95f90e5f9 100644 --- a/clients/drcachesim/tests/allasm-arm.templatex +++ b/clients/drcachesim/tests/allasm-arm.templatex @@ -11,6 +11,7 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: [45][90][0-9] Misses: [5-9] + Invalidations: 0 Flushes: 1 Prefetch hits: 1 Prefetch misses: 1 @@ -18,6 +19,7 @@ Core #0 \(1 thread\(s\)\) L1D stats: Hits: 1[0-9] Misses: [1-9] + Invalidations: 0 Prefetch hits: 1 Prefetch misses: 3 Miss rate: [ 1][0-3][,\.]..% @@ -27,6 +29,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: 1 Misses: [ 1][0-9] + Invalidations: 0 Flushes: 1 Prefetch hits: 1 Prefetch misses: 3 diff --git a/clients/drcachesim/tests/allasm-thumb.templatex b/clients/drcachesim/tests/allasm-thumb.templatex index c361f04be31..35496cd2bab 100644 --- a/clients/drcachesim/tests/allasm-thumb.templatex +++ b/clients/drcachesim/tests/allasm-thumb.templatex @@ -11,10 +11,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: 6[34]. Misses: 11 + Invalidations: 0 Miss rate: 1[,\.]69% L1D stats: Hits: 3[0-9] Misses: *[0-9]* + Invalidations: 0 Prefetch hits: 1 Prefetch misses: 6 Miss rate: [ 1][0-5][,\.]..% @@ -24,6 +26,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: 3 Misses: 1[0-9] + Invalidations: 0 Prefetch hits: 1 Prefetch misses: [56] Local miss rate: [89].[,\.]..% diff --git a/clients/drcachesim/tests/delay-simple.templatex b/clients/drcachesim/tests/delay-simple.templatex index 121436d900b..971c7a78467 100644 --- a/clients/drcachesim/tests/delay-simple.templatex +++ b/clients/drcachesim/tests/delay-simple.templatex @@ -6,10 +6,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[0-9,\.]*% L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[0-9,\.]*% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -17,6 +19,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9,\.]*% Child hits: *[0-9,\.]*. Total miss rate: *[0-9,\.]*% diff --git a/clients/drcachesim/tests/filter-no-d.templatex b/clients/drcachesim/tests/filter-no-d.templatex index 020e79591f9..353580e74ef 100644 --- a/clients/drcachesim/tests/filter-no-d.templatex +++ b/clients/drcachesim/tests/filter-no-d.templatex @@ -5,16 +5,19 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[1-9][0-9][,\.]..% L1D stats: Hits: 0 Misses: 0 + Invalidations: 0 Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[1-9][0-9][,\.]..% Child hits: *[0-9,\.]*. Total miss rate: *[1-9][0-9][,\.]..% diff --git a/clients/drcachesim/tests/filter-no-i.templatex b/clients/drcachesim/tests/filter-no-i.templatex index b7702e32c1b..9bbda524c70 100644 --- a/clients/drcachesim/tests/filter-no-i.templatex +++ b/clients/drcachesim/tests/filter-no-i.templatex @@ -5,9 +5,11 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: 0 Misses: 0 + Invalidations: 0 L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[1-9][0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -15,6 +17,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[1-9][0-9][,\.]..% Child hits: *[0-9,\.]*. Total miss rate: *[1-9][0-9][,\.]..% diff --git a/clients/drcachesim/tests/filter-simple.templatex b/clients/drcachesim/tests/filter-simple.templatex index 85aba144c7e..ea0c7b2c16c 100644 --- a/clients/drcachesim/tests/filter-simple.templatex +++ b/clients/drcachesim/tests/filter-simple.templatex @@ -5,10 +5,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[1-9][0-9][,\.]..% L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[1-9][0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -16,6 +18,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[1-9][0-9][,\.]..% Child hits: *[0-9,\.]*. Total miss rate: *[1-9][0-9][,\.]..% diff --git a/clients/drcachesim/tests/multiproc.templatex b/clients/drcachesim/tests/multiproc.templatex index 3941c42a555..51adece4a0d 100644 --- a/clients/drcachesim/tests/multiproc.templatex +++ b/clients/drcachesim/tests/multiproc.templatex @@ -5,25 +5,30 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9]*[,\.]?...[,\.]?... Misses: *[0-9,\.]* + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9]*[,\.]?...[,\.]?... Misses: *[0-9\.,]* + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(1 thread\(s\)\) L1I stats: Hits: *[0-9]*[,\.]?...[,\.]?... Misses: *[0-9,\.]* + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9]*[,\.]?...[,\.]?... Misses: *[0-9]*[,\.]?... + Invalidations: *0 .* Miss rate: *[0-9]*[,\.]..% Core #2 \(0 thread\(s\)\) Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9]* Misses: *[0-9]*[,\.]?... + Invalidations: *0 .* Local miss rate: *[1-9][0-9][,\.]..% Child hits: *[0-9,\.]*[,\.]?...[,\.]?... Total miss rate: [0-9][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_client.templatex b/clients/drcachesim/tests/offline-burst_client.templatex index 6082fec7bf7..3b2909b1f20 100644 --- a/clients/drcachesim/tests/offline-burst_client.templatex +++ b/clients/drcachesim/tests/offline-burst_client.templatex @@ -27,10 +27,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -38,6 +40,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-1][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_maps.templatex b/clients/drcachesim/tests/offline-burst_maps.templatex index cd97a4efe06..0467e29ec8b 100644 --- a/clients/drcachesim/tests/offline-burst_maps.templatex +++ b/clients/drcachesim/tests/offline-burst_maps.templatex @@ -15,10 +15,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -26,6 +28,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-1][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_noreach.templatex b/clients/drcachesim/tests/offline-burst_noreach.templatex index cd97a4efe06..0467e29ec8b 100644 --- a/clients/drcachesim/tests/offline-burst_noreach.templatex +++ b/clients/drcachesim/tests/offline-burst_noreach.templatex @@ -15,10 +15,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -26,6 +28,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-1][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_replace.templatex b/clients/drcachesim/tests/offline-burst_replace.templatex index c078224cfe1..722f16494d1 100644 --- a/clients/drcachesim/tests/offline-burst_replace.templatex +++ b/clients/drcachesim/tests/offline-burst_replace.templatex @@ -19,10 +19,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -30,6 +32,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-1][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_replaceall.templatex b/clients/drcachesim/tests/offline-burst_replaceall.templatex index 062a3107e6b..aae944b87c4 100644 --- a/clients/drcachesim/tests/offline-burst_replaceall.templatex +++ b/clients/drcachesim/tests/offline-burst_replaceall.templatex @@ -10,10 +10,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -21,6 +23,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-1][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_static.templatex b/clients/drcachesim/tests/offline-burst_static.templatex index 67050ac40cd..441e4efd86d 100644 --- a/clients/drcachesim/tests/offline-burst_static.templatex +++ b/clients/drcachesim/tests/offline-burst_static.templatex @@ -24,10 +24,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*..... Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: 0[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -35,6 +37,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-1][,\.]..% diff --git a/clients/drcachesim/tests/offline-burst_threads.templatex b/clients/drcachesim/tests/offline-burst_threads.templatex index 3a80e8b25d3..3aed671ef01 100644 --- a/clients/drcachesim/tests/offline-burst_threads.templatex +++ b/clients/drcachesim/tests/offline-burst_threads.templatex @@ -15,16 +15,19 @@ Cache simulation results: Core #0 \([0-9] traced CPU\(s\): [#0-9, ]+\) L1I stats: Hits: *[0-9,\.]* - Misses: *[0-9,\.]*.* + Misses: *[0-9,\.]* + Invalidations: *0.* L1D stats: Hits: *[0-9,\.]* - Misses: *[0-9,\.]*.* + Misses: *[0-9,\.]* + Invalidations: *0.* Core #1 \([0-9] traced CPU\(s\).* Core #2 \([0-9] traced CPU\(s\).* Core #3 \([0-9] traced CPU\(s\).* LL stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 .* Local miss rate: *[0-9,\.]*% Child hits: *[0-9,\.]* Total miss rate: *[0-9,\.]*% diff --git a/clients/drcachesim/tests/offline-filter.templatex b/clients/drcachesim/tests/offline-filter.templatex index dd6f5571414..f738be8851e 100644 --- a/clients/drcachesim/tests/offline-filter.templatex +++ b/clients/drcachesim/tests/offline-filter.templatex @@ -4,10 +4,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[0-9][0-9][,\.]..% L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]*. + Invalidations: *0 .* Miss rate: *[0-9][0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -15,6 +17,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*. Misses: *[0-9,\.]*.. + Invalidations: *0 .* Local miss rate: *[0-9][0-9][,\.]..% Child hits: *[0-9,\.]*. Total miss rate: *[0-9][0-9][,\.]..% diff --git a/clients/drcachesim/tests/offline-multiproc.templatex b/clients/drcachesim/tests/offline-multiproc.templatex index 62cfabf49b2..3a5b9b9d944 100644 --- a/clients/drcachesim/tests/offline-multiproc.templatex +++ b/clients/drcachesim/tests/offline-multiproc.templatex @@ -4,10 +4,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9\.,]* Misses: *[0-9,\.]* + Invalidations: *0 .* Miss rate: *[0-9]*[,\.]..% L1D stats: Hits: *[0-9\.,]* Misses: *[0-9\.,]* + Invalidations: *0 .* Miss rate: *[0-9]*[,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -15,6 +17,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9\.,]* Misses: *[0-9\.,]* + Invalidations: *0 .* Local miss rate: *[0-9]*[,\.]..% Child hits: *[0-9\.,]* Total miss rate: *[0-9]*[,\.]..% diff --git a/clients/drcachesim/tests/offline-simple.templatex b/clients/drcachesim/tests/offline-simple.templatex index 070c4f54a80..4acf07c0a73 100644 --- a/clients/drcachesim/tests/offline-simple.templatex +++ b/clients/drcachesim/tests/offline-simple.templatex @@ -4,10 +4,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*... Misses: *[0-9,\.]*.. + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9,\.]*... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: [0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -15,6 +17,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*... Misses: *[0-9,\.]*... + Invalidations: *0 .* Local miss rate: [0-9].[,\.]..% Child hits: *[0-9,\.]*... Total miss rate: [0-4][,\.]..% diff --git a/clients/drcachesim/tests/phys.templatex b/clients/drcachesim/tests/phys.templatex index d76093ff9db..aae6f4aedab 100644 --- a/clients/drcachesim/tests/phys.templatex +++ b/clients/drcachesim/tests/phys.templatex @@ -5,10 +5,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9]*[,\.]?... Misses: *[0-9]..? + Invalidations: *0 .* Miss rate: 0[,\.]..% L1D stats: Hits: *[0-9].[,\.]?... Misses: *[0-9]*[,\.]?..?.? + Invalidations: *0 .* Miss rate: [0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -16,6 +18,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9]..? Misses: *[0-9]*[,\.]?..?.? + Invalidations: *0 .* Local miss rate: [0-9].[,\.]..% Child hits: *([3-9]|[1-9].).[,\.]?... Total miss rate: [0-2][,\.]..% diff --git a/clients/drcachesim/tests/simple.templatex b/clients/drcachesim/tests/simple.templatex index f1be32c8816..e2f89f6d25f 100644 --- a/clients/drcachesim/tests/simple.templatex +++ b/clients/drcachesim/tests/simple.templatex @@ -5,10 +5,12 @@ Core #0 \(1 thread\(s\)\) L1I stats: Hits: *[0-9,\.]*.... Misses: *[0-9,\.]*.. + Invalidations: *0 .* Miss rate: [0-1][,\.]..% L1D stats: Hits: *[0-9,\.]*.... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: [0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -16,6 +18,7 @@ Core #3 \(0 thread\(s\)\) LL stats: Hits: *[0-9,\.]*.. Misses: *[0-9,\.]*... + Invalidations: *0 .* Local miss rate: [0-9].[,\.]..% Child hits: *[0-9,\.]*..... Total miss rate: [0-3][,\.]..% diff --git a/clients/drcachesim/tests/threads.templatex b/clients/drcachesim/tests/threads.templatex index 5c93e094ef5..491eec6a039 100644 --- a/clients/drcachesim/tests/threads.templatex +++ b/clients/drcachesim/tests/threads.templatex @@ -69,10 +69,12 @@ Core #0 \([0-9] traced CPU\(s\): [#0-9, ]+\) L1I stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 .* Miss rate: *[0-9,\.]*% L1D stats: Hits: *[0-9,\.]* Misses: *[0-9,\.]* + Invalidations: *0 .* Miss rate: *[0-9,\.]*% Core #1 \([0-9] traced CPU\(s\).* Core #2 \([0-9] traced CPU\(s\).* @@ -80,6 +82,7 @@ Core #3 \([0-9] traced CPU\(s\).* LL stats: Hits: *[0-9,\.]*... Misses: *[0-9,\.]*... + Invalidations: *0 .* Local miss rate: *[0-9]*[\.,]..% Child hits: *[0-9,\.]*...... Total miss rate: 0[\.,]..% diff --git a/clients/drcachesim/tests/warmup-valid.templatex b/clients/drcachesim/tests/warmup-valid.templatex index a231e78b32a..3131318cc01 100644 --- a/clients/drcachesim/tests/warmup-valid.templatex +++ b/clients/drcachesim/tests/warmup-valid.templatex @@ -7,12 +7,14 @@ Core #0 \(1 thread\(s\)\) Warmup misses: *[0-9,\.]*.. Hits: *[0-9,\.]*.... Misses: *[0-9,\.]*.. + Invalidations: *0 .* Miss rate: [0-1][,\.]..% L1D stats: Warmup hits: *[0-9,\.]*.. Warmup misses: *[0-9,\.]*.. Hits: *[0-9,\.]*.... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: [0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -22,6 +24,7 @@ LL stats: Warmup misses: *[0-9,\.]*.. Hits: *[0-9,\.]*.. Misses: *[0-9,\.]*... + Invalidations: *0 .* Local miss rate: [0-9].[,\.]..% Child hits: *[0-9,\.]*..... Total miss rate: [0-3][,\.]..% diff --git a/clients/drcachesim/tests/warmup-zeros.templatex b/clients/drcachesim/tests/warmup-zeros.templatex index a1cbb2eceab..05c77be7758 100644 --- a/clients/drcachesim/tests/warmup-zeros.templatex +++ b/clients/drcachesim/tests/warmup-zeros.templatex @@ -7,12 +7,14 @@ Core #0 \(1 thread\(s\)\) Warmup misses: *[0]*.. Hits: *[0-9,\.]*.... Misses: *[0-9,\.]*.. + Invalidations: *0 .* Miss rate: [0-1][,\.]..% L1D stats: Warmup hits: *[0]*.. Warmup misses: *[0]*.. Hits: *[0-9,\.]*.... Misses: *[0-9,\.]*... + Invalidations: *0 .* Miss rate: [0-9][,\.]..% Core #1 \(0 thread\(s\)\) Core #2 \(0 thread\(s\)\) @@ -22,6 +24,7 @@ LL stats: Warmup misses: *[0]*.. Hits: *[0-9,\.]*.. Misses: *[0-9,\.]*... + Invalidations: *0 .* Local miss rate: [0-9].[,\.]..% Child hits: *[0-9,\.]*..... Total miss rate: [0-3][,\.]..%