diff --git a/src/adc.rs b/src/adc.rs
index 2dca2be..88271a3 100644
--- a/src/adc.rs
+++ b/src/adc.rs
@@ -387,13 +387,12 @@ macro_rules! hal {
                             } else if #[cfg(feature = "f4")] {
                                 rcc_en_reset!(2, [<adc $rcc_num>], rcc);
                             } else if #[cfg(feature = "h7")] {
-                                match device {
-                                    AdcDevice::One | AdcDevice::Two => {
-                                        rcc.ahb1enr.modify(|_, w| w.adc12en().set_bit());
-                                    }
-                                    AdcDevice::Three => {
-                                        rcc.ahb4enr.modify(|_, w| w.adc3en().set_bit());
-                                    }
+                                if device == AdcDevice::One || device == AdcDevice::Two {
+                                    rcc.ahb1enr.modify(|_, w| w.adc12en().set_bit());
+                                }
+                            } else if #[cfg(all(feature = "h7", not(feature = "h7b3")))] {
+                                if device == AdcDevice::Three {
+                                    rcc.ahb4enr.modify(|_, w| w.adc3en().set_bit());
                                 }
                             } else if #[cfg(any(feature = "g4"))] {
                                 rcc.ahb2enr.modify(|_, w| w.adc12en().set_bit());
@@ -1228,11 +1227,16 @@ hal!(ADC3, ADC_COMMON, adc3, _);
 #[cfg(any(feature = "l5"))]
 hal!(ADC, ADC_COMMON, adc1, _);
 
-// todo Implement ADC3 on H7. The issue is the enable / reset being on ahb4.
 cfg_if! {
     if #[cfg(feature = "h7")] {
         hal!(ADC1, ADC12_COMMON, adc1, 12);
         hal!(ADC2, ADC12_COMMON, adc2, 12);
+    }
+}
+
+// todo Implement ADC3 on H7. The issue is the enable / reset being on ahb4.
+cfg_if! {
+    if #[cfg(all(feature = "h7", not(feature = "h7b3")))] {
         hal!(ADC3, ADC3_COMMON, adc3, 3);
     }
 }
diff --git a/src/clocks/h.rs b/src/clocks/h.rs
index 88a7392..38683f5 100644
--- a/src/clocks/h.rs
+++ b/src/clocks/h.rs
@@ -539,7 +539,7 @@ impl Clocks {
                 // 3. Reset the ODEN bit in the SYSCFG_PWRCR register to disable VOS0.
             }
             _ => {
-                #[cfg(feature = "h7")]
+                #[cfg(all(feature = "h7", not(feature = "h7b3")))]
                 pwr.d3cr
                     .modify(|_, w| unsafe { w.vos().bits(self.vos_range as u8) });
                 #[cfg(feature = "h5")]
@@ -627,20 +627,20 @@ impl Clocks {
             w.stopwuck().bit(self.stop_wuck as u8 != 0)
         });
 
-        #[cfg(feature = "h7")]
+        #[cfg(all(feature = "h7", not(feature = "h7b3")))]
         rcc.d1cfgr.modify(|_, w| unsafe {
             w.d1cpre().bits(self.d1_core_prescaler as u8);
             w.d1ppre().bits(self.d1_prescaler as u8);
             w.hpre().bits(self.hclk_prescaler as u8)
         });
 
-        #[cfg(feature = "h7")]
+        #[cfg(all(feature = "h7", not(feature = "h7b3")))]
         rcc.d2cfgr.modify(|_, w| unsafe {
             w.d2ppre1().bits(self.d2_prescaler1 as u8);
             w.d2ppre2().bits(self.d2_prescaler2 as u8)
         });
 
-        #[cfg(feature = "h7")]
+        #[cfg(all(feature = "h7", not(feature = "h7b3")))]
         rcc.d3cfgr
             .modify(|_, w| unsafe { w.d3ppre().bits(self.d3_prescaler as u8) });
 
diff --git a/src/crc.rs b/src/crc.rs
index 6cac30c..19e16a7 100644
--- a/src/crc.rs
+++ b/src/crc.rs
@@ -29,7 +29,7 @@ impl CrcExt for CRC {
                 rcc.ahb1enr.modify(|_, w| w.crcen().set_bit());
                 rcc.ahb1rstr.modify(|_, w| w.crcrst().set_bit());
                 rcc.ahb1rstr.modify(|_, w| w.crcrst().clear_bit());
-            } else { // H7
+            } else if #[cfg(not(feature = "h7b3"))] { // H7
                 rcc.ahb4enr.modify(|_, w| w.crcen().set_bit());
                 rcc.ahb4rstr.modify(|_, w| w.crcrst().set_bit());
                 rcc.ahb4rstr.modify(|_, w| w.crcrst().clear_bit());
diff --git a/src/lib.rs b/src/lib.rs
index b4b8674..0c3f56a 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -632,7 +632,11 @@ pub fn debug_workaround() {
     let dbgmcu = unsafe { &(*pac::DBGMCU::ptr()) };
 
     cfg_if! {
-        if #[cfg(all(feature = "h7", not(any(feature = "h747cm4", feature = "h747cm7"))))] {
+        if #[cfg(feature = "h7b3")] {
+            dbgmcu.cr.modify(|_, w| w.dbgsleep_cd().set_bit());
+            dbgmcu.cr.modify(|_, w| w.dbgstop_cd().set_bit());
+            dbgmcu.cr.modify(|_, w| w.dbgstby_cd().set_bit());
+        } else if #[cfg(all(feature = "h7", not(any(feature = "h747cm4", feature = "h747cm7"))))] {
             dbgmcu.cr.modify(|_, w| w.dbgsleep_d1().set_bit());
             dbgmcu.cr.modify(|_, w| w.dbgstop_d1().set_bit());
             dbgmcu.cr.modify(|_, w| w.dbgstby_d1().set_bit());
diff --git a/src/util.rs b/src/util.rs
index 18c0458..9984874 100644
--- a/src/util.rs
+++ b/src/util.rs
@@ -589,7 +589,7 @@ impl RccPeriph for pac::SAI2 {
     }
 }
 
-#[cfg(all(feature = "h7", not(feature = "h735")))]
+#[cfg(all(feature = "h7", not(any(feature = "h735", feature = "h7b3"))))]
 impl RccPeriph for pac::SAI3 {
     fn en_reset(rcc: &RegisterBlock) {
         rcc_en_reset!(apb2, sai3, rcc);
@@ -616,7 +616,7 @@ impl RccPeriph for pac::SAI3 {
     }
 }
 
-#[cfg(feature = "h7")]
+#[cfg(all(feature = "h7", not(feature = "h7b3")))]
 impl RccPeriph for pac::SAI4 {
     fn en_reset(rcc: &RegisterBlock) {
         rcc_en_reset!(apb4, sai4, rcc);