From c6cc878660091ddee33fb41f1f78c80b5247f9e8 Mon Sep 17 00:00:00 2001 From: David O'Connor Date: Sun, 17 Dec 2023 09:16:39 -0500 Subject: [PATCH] Fixed errors with VCO speed checking on H7 --- examples/adc.rs | 1 - examples/can-send.rs | 9 +-- examples/can.rs | 14 ++--- examples/clock_cfg.rs | 1 - examples/comp.rs | 6 +- examples/flash.rs | 1 - examples/gpio.rs | 4 +- examples/i2c.rs | 1 - examples/interrupts.rs | 1 - examples/pdm_mic_dac_output.rs | 6 +- examples/rtc.rs | 1 - examples/serial_nonblocking.rs | 1 - examples/spi.rs | 1 - examples/spi_imu_filtered.rs | 17 ++---- examples/timer.rs | 1 - examples/usb_serial.rs | 3 - examples/waveform_generator.rs | 7 +-- src/adc.rs | 19 +++--- src/can.rs | 4 +- src/clocks/baseline.rs | 9 ++- src/clocks/f.rs | 4 +- src/clocks/h.rs | 15 +++-- src/comp.rs | 12 ++-- src/crc.rs | 7 +-- src/dac.rs | 13 ++--- src/dfsdm.rs | 12 ++-- src/dma.rs | 8 +-- src/ethernet.rs | 1 - src/flash/mod.rs | 4 +- src/flash/non_trustzone.rs | 8 +-- src/flash/trustzone.rs | 3 +- src/gpio.rs | 12 ++-- src/hsem.rs | 5 +- src/i2c.rs | 20 +++---- src/i2c_f4.rs | 4 +- src/ipcc.rs | 4 +- src/iwdg.rs | 1 - src/lib.rs | 102 +++++++-------------------------- src/low_power.rs | 15 ++--- src/rng.rs | 3 +- src/rtc.rs | 4 +- src/sai.rs | 28 ++++----- src/spi.rs | 16 +++--- src/timer.rs | 31 ++++------ src/usart.rs | 35 +++++------ src/usb.rs | 12 ++-- src/usb_otg.rs | 8 +-- src/util.rs | 19 +++--- 48 files changed, 180 insertions(+), 333 deletions(-) diff --git a/examples/adc.rs b/examples/adc.rs index 7afd47d..9bef2c9 100644 --- a/examples/adc.rs +++ b/examples/adc.rs @@ -12,7 +12,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal2::{ adc::{ Adc, AdcChannel, AdcDevice, AdcInterrupt, Align, ClockMode, InputType, OperationMode, diff --git a/examples/can-send.rs b/examples/can-send.rs index d93cb9e..cacdf42 100644 --- a/examples/can-send.rs +++ b/examples/can-send.rs @@ -4,13 +4,12 @@ #![no_std] #![no_main] -use bxcan::{ - filter::Mask32, - {Frame, StandardId}, -}; use core::panic::PanicInfo; + +use bxcan::{filter::Mask32, Frame, StandardId}; use cortex_m::delay::Delay; use cortex_m_rt::entry; // The runtime +use defmt_rtt as _; use nb::block; use stm32_hal2::{ self, @@ -20,8 +19,6 @@ use stm32_hal2::{ pac, }; -use defmt_rtt as _; - // This marks the entrypoint of our application. The cortex_m_rt creates some // startup code before this, but we don't need to worry about this #[entry] diff --git a/examples/can.rs b/examples/can.rs index f03fee2..0de35e9 100644 --- a/examples/can.rs +++ b/examples/can.rs @@ -11,20 +11,18 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - -use stm32_hal2::{ - can::{self, Can}, - clocks::Clocks, - gpio::{self, Edge, OutputSpeed, Pin, PinMode, PinState, Port}, - pac, -}; - use fdcan::{ frame::{FrameFormat, TxFrameHeader}, id::{ExtendedId, Id}, interrupt::{Interrupt, InterruptLine}, FdCan, NormalOperationMode, }; +use stm32_hal2::{ + can::{self, Can}, + clocks::Clocks, + gpio::{self, Edge, OutputSpeed, Pin, PinMode, PinState, Port}, + pac, +}; // Code shortener to isolate typestate syntax. type Can_ = FdCan; diff --git a/examples/clock_cfg.rs b/examples/clock_cfg.rs index 845e238..eacb34f 100644 --- a/examples/clock_cfg.rs +++ b/examples/clock_cfg.rs @@ -10,7 +10,6 @@ #![no_std] use cortex_m_rt::entry; - use stm32_hal2::{ clocks::{self, ApbPrescaler, Clocks, InputSrc, MsiRng, PllCfg, PllSrc, Pllm, Pllr}, low_power, pac, diff --git a/examples/comp.rs b/examples/comp.rs index aa00a52..9369def 100644 --- a/examples/comp.rs +++ b/examples/comp.rs @@ -5,13 +5,11 @@ #![no_std] // These lines are part of our setup for debug printing. -use defmt_rtt as _; -use panic_probe as _; - // Cortex-M Import use cortex_m::delay::Delay; use cortex_m_rt::entry; - +use defmt_rtt as _; +use panic_probe as _; // Importing library use stm32_hal2::{ clocks::Clocks, diff --git a/examples/flash.rs b/examples/flash.rs index 31bf3c8..c168daa 100644 --- a/examples/flash.rs +++ b/examples/flash.rs @@ -10,7 +10,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal2::{ clocks::Clocks, flash::{Bank, Flash}, diff --git a/examples/gpio.rs b/examples/gpio.rs index ae5c7d3..2bf4a42 100644 --- a/examples/gpio.rs +++ b/examples/gpio.rs @@ -15,7 +15,7 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - +use embedded_hal::digital::OutputPin; use stm32_hal2::{ adc::{Adc, AdcChannel, Align, CkMode, InputType, OperationMode}, clocks::Clocks, @@ -24,8 +24,6 @@ use stm32_hal2::{ prelude::*, }; -use embedded_hal::digital::OutputPin; - // Set up an output pin in a globally-accessible mutex. This is useful for accessing // peripherals in interrupt contexts. We use a macro imported in the // `prelude` module to simplify this syntax, and accessing it later. diff --git a/examples/i2c.rs b/examples/i2c.rs index 637ee55..1c19ebc 100644 --- a/examples/i2c.rs +++ b/examples/i2c.rs @@ -13,7 +13,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal2::{ clocks::Clocks, dma::{self, Dma, DmaChannel, DmaInterrupt, DmaPeriph, DmaWriteBuf}, diff --git a/examples/interrupts.rs b/examples/interrupts.rs index 5871e02..a13421e 100644 --- a/examples/interrupts.rs +++ b/examples/interrupts.rs @@ -10,7 +10,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal::{ adc::{Adc, AdcChannel, AdcDevice}, clocks::Clocks, diff --git a/examples/pdm_mic_dac_output.rs b/examples/pdm_mic_dac_output.rs index 04e600b..228cae2 100644 --- a/examples/pdm_mic_dac_output.rs +++ b/examples/pdm_mic_dac_output.rs @@ -35,7 +35,8 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - +use defmt_rtt as _; // global logger +use panic_probe as _; use stm32_hal2::{ self, clocks::{Clocks, HclkPrescaler, InputSrc, PllCfg, PllSrc, SaiSrc, VosRange}, @@ -49,9 +50,6 @@ use stm32_hal2::{ timer::{BasicTimer, MasterModeSelection, Timer, TimerInterrupt}, }; -use defmt_rtt as _; // global logger -use panic_probe as _; - const FS: u32 = 48_000; const BLOCK_SIZE: usize = 500; // 1000 @ 48kHz = 21ms diff --git a/examples/rtc.rs b/examples/rtc.rs index 8276e21..545a502 100644 --- a/examples/rtc.rs +++ b/examples/rtc.rs @@ -14,7 +14,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal::{ clocks::Clocks, low_power::{self, StopMode}, diff --git a/examples/serial_nonblocking.rs b/examples/serial_nonblocking.rs index 253dd1e..f948459 100644 --- a/examples/serial_nonblocking.rs +++ b/examples/serial_nonblocking.rs @@ -16,7 +16,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal2::{ clocks::Clocks, dma::{self, Dma, DmaChannel, DmaConfig, DmaPeriph}, diff --git a/examples/spi.rs b/examples/spi.rs index 4fa713c..f256f9f 100644 --- a/examples/spi.rs +++ b/examples/spi.rs @@ -13,7 +13,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal2::{ clocks::Clocks, dma::{self, Dma, DmaChannel, DmaInput, DmaInterrupt, DmaPeriph, DmaWriteBuf}, diff --git a/examples/spi_imu_filtered.rs b/examples/spi_imu_filtered.rs index 476fe88..3526bb4 100644 --- a/examples/spi_imu_filtered.rs +++ b/examples/spi_imu_filtered.rs @@ -5,8 +5,12 @@ #![no_main] #![no_std] +use cmsis_dsp_api as dsp_api; +use cmsis_dsp_sys as dsp_sys; use cortex_m::{self, asm, delay::Delay}; - +use defmt::println; +use defmt_rtt as _; // global logger +use panic_probe as _; use stm32_hal2::{ clocks::{self, Clocks}, dma::{self, ChannelCfg, Dma, DmaChannel, DmaInterrupt, DmaPeriph}, @@ -15,14 +19,6 @@ use stm32_hal2::{ spi::{BaudRate, Spi, SpiConfig, SpiMode}, }; -use cmsis_dsp_api as dsp_api; -use cmsis_dsp_sys as dsp_sys; - -use defmt::println; - -use defmt_rtt as _; // global logger -use panic_probe as _; - static mut WRITE_BUF: [u8; 13] = [0; 13]; // IMU readings buffer. 3 accelerometer, and 3 gyro measurements; 2 bytes each. 0-padded on the left, @@ -37,6 +33,7 @@ pub struct IirInstWrapper { unsafe impl Send for IirInstWrapper {} mod imu { + use cortex_m::delay::Delay; ///! Module for TDK ICM-426xx IMUs. Stripped down in this example to include only what we need. use stm32_hal2::{ dma::{Dma, DmaChannel, DmaPeriph}, @@ -45,8 +42,6 @@ mod imu { spi::Spi, }; - use cortex_m::delay::Delay; - const GYRO_FULLSCALE: f32 = 34.90659; // 2,000 degrees/sec const ACCEL_FULLSCALE: f32 = 156.9056; // 16 G diff --git a/examples/timer.rs b/examples/timer.rs index 7a845fc..f91c504 100644 --- a/examples/timer.rs +++ b/examples/timer.rs @@ -9,7 +9,6 @@ use cortex_m::{ peripheral::NVIC, }; use cortex_m_rt::entry; - use stm32_hal2::{ clocks::Clocks, gpio::{Edge, Pin, PinMode, Port}, diff --git a/examples/usb_serial.rs b/examples/usb_serial.rs index ffbc436..dd319be 100644 --- a/examples/usb_serial.rs +++ b/examples/usb_serial.rs @@ -6,16 +6,13 @@ #![no_std] use cortex_m::{self, interrupt::free, peripheral::NVIC}; - use cortex_m_rt::entry; - use stm32_hal2::{ clocks::{self, Clk48Src, Clocks, CrsSyncSrc}, gpio::{Pin, PinMode, Port}, pac, usb::{Peripheral, UsbBus, UsbBusType}, }; - use usbd_serial::{SerialPort, USB_CLASS_CDC}; static mut USB_BUS: Option> = None; diff --git a/examples/waveform_generator.rs b/examples/waveform_generator.rs index 26de3ab..a4313f5 100644 --- a/examples/waveform_generator.rs +++ b/examples/waveform_generator.rs @@ -26,9 +26,9 @@ use cortex_m::{ interrupt::{free, Mutex}, peripheral::NVIC, }; - use cortex_m_rt::entry; - +use defmt_rtt as _; // global logger +use panic_probe as _; use stm32_hal2::{ self, clocks::Clocks, @@ -40,9 +40,6 @@ use stm32_hal2::{ timer::{BasicTimer, MasterModeSelection, TimerDevice}, }; -use defmt_rtt as _; // global logger -use panic_probe as _; - // Length of the lookup table used to generate sin waves etc. const LUT_LEN: usize = 256; diff --git a/src/adc.rs b/src/adc.rs index 5db8436..ba886b0 100644 --- a/src/adc.rs +++ b/src/adc.rs @@ -1,23 +1,20 @@ //! Support for the ADC (Analog to Digital Converter) peripheral. -use cortex_m::{asm, delay::Delay, interrupt::free}; - use core::ptr; -use crate::{ - clocks::Clocks, - pac::{self, RCC}, - util::rcc_en_reset, -}; - use cfg_if::cfg_if; +use cortex_m::{asm, delay::Delay, interrupt::free}; use paste::paste; -#[cfg(not(any(feature = "f4", feature = "l552", feature = "h5")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - #[cfg(any(feature = "f3", feature = "l4"))] use crate::dma::DmaInput; +#[cfg(not(any(feature = "f4", feature = "l552", feature = "h5")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; +use crate::{ + clocks::Clocks, + pac::{self, RCC}, + util::rcc_en_reset, +}; // Address of the ADCinterval voltage reference. This address is found in the User manual. It appears // to be the same for most STM32s. The voltage this is measured at my vary by variant; eg 3.0 vice 3.3. diff --git a/src/can.rs b/src/can.rs index 3fa2957..6f958c3 100644 --- a/src/can.rs +++ b/src/can.rs @@ -3,10 +3,10 @@ //! //! Requires the `can_bx` or `can_fd_g[h]` features. F3, F4, and L4 use BX CAN. G0, G4, L5, and H7 use FD CAN. -use crate::{pac::RCC, util::rcc_en_reset}; - use cfg_if::cfg_if; +use crate::{pac::RCC, util::rcc_en_reset}; + // todo: H5 support. cfg_if! { diff --git a/src/clocks/baseline.rs b/src/clocks/baseline.rs index 2d3bde2..fb8334a 100644 --- a/src/clocks/baseline.rs +++ b/src/clocks/baseline.rs @@ -4,6 +4,10 @@ // Similar in from to the H7 clocks module, but includes notable differendes. +use cfg_if::cfg_if; + +#[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "g4"))] +use crate::pac::CRS; use crate::{ clocks::RccError, pac::{self, FLASH, RCC}, @@ -11,11 +15,6 @@ use crate::{ MAX_ITERS, }; -#[cfg(any(feature = "l4", feature = "l5", feature = "wb", feature = "g4"))] -use crate::pac::CRS; - -use cfg_if::cfg_if; - // todo: WB is missing second LSI2, and perhaps other things. #[cfg(not(any(feature = "g0", feature = "wl")))] diff --git a/src/clocks/f.rs b/src/clocks/f.rs index e813572..5fc00d4 100644 --- a/src/clocks/f.rs +++ b/src/clocks/f.rs @@ -1,11 +1,11 @@ +use cfg_if::cfg_if; + use crate::{ clocks::RccError, pac::{self, FLASH, RCC}, util::rcc_en_reset, }; -use cfg_if::cfg_if; - cfg_if! { if #[cfg(feature = "f3")] { #[derive(Clone, Copy)] diff --git a/src/clocks/h.rs b/src/clocks/h.rs index 8329078..0b28e46 100644 --- a/src/clocks/h.rs +++ b/src/clocks/h.rs @@ -4,17 +4,16 @@ // Similar in from to the `baseline` clocks module, but includes notable differendes. +use cfg_if::cfg_if; + +#[cfg(not(any(feature = "h5", feature = "h7b3", feature = "h735")))] +use crate::pac::SYSCFG; use crate::{ clocks::RccError, pac::{CRS, FLASH, PWR, RCC}, MAX_ITERS, }; -#[cfg(not(any(feature = "h5", feature = "h7b3", feature = "h735")))] -use crate::pac::SYSCFG; - -use cfg_if::cfg_if; - #[derive(Clone, Copy, PartialEq)] pub enum PllSrc { None, @@ -1234,13 +1233,13 @@ impl Clocks { // Note: The RM appears out of date: Revision "V" allgedly supports 960_000_000 // VCO speed, to allow a max core speed of 480Mhz. let vco_speed = self.vco_output_freq(self.pll_src, 1); - if pll_input_speed <= 2_000_000 && (vco_speed < 192_000_000 || vco_speed > 960_000_000) - { + if pll_input_speed > 2_000_000 && (vco_speed < 192_000_000 || vco_speed > 960_000_000) { return Err(RccError::Speed); } // 1: Medium VCO range: 150 to 420 MHz. (VCOL) // Note: You may get power savings - if pll_input_speed > 2_000_000 && (vco_speed < 150_000_000 || vco_speed > 420_000_000) { + if pll_input_speed <= 2_000_000 && (vco_speed < 150_000_000 || vco_speed > 420_000_000) + { return Err(RccError::Speed); } } diff --git a/src/comp.rs b/src/comp.rs index 27d1e93..f6739fd 100644 --- a/src/comp.rs +++ b/src/comp.rs @@ -10,20 +10,16 @@ use core::marker::PhantomData; -use crate::pac; - -use paste::paste; - use cfg_if::cfg_if; +use paste::paste; +use crate::pac; #[cfg(any(feature = "g473"))] use crate::pac::comp::{C1CSR, C2CSR, C3CSR, C4CSR, C5CSR, C6CSR, C7CSR}; - -#[cfg(any(feature = "h747cm4", feature = "h747cm7"))] -use crate::pac::comp1::{CFGR1, CFGR2}; - #[cfg(any(feature = "l4x6"))] use crate::pac::comp::{COMP1_CSR, COMP2_CSR}; +#[cfg(any(feature = "h747cm4", feature = "h747cm7"))] +use crate::pac::comp1::{CFGR1, CFGR2}; // Config enums /// Comparator power mode diff --git a/src/crc.rs b/src/crc.rs index 7262095..6cac30c 100644 --- a/src/crc.rs +++ b/src/crc.rs @@ -2,13 +2,12 @@ // Based on `stm32h7xx-hal` -use core::convert::TryInto; -use core::fmt; - -use crate::pac::{CRC, RCC}; +use core::{convert::TryInto, fmt}; use cfg_if::cfg_if; +use crate::pac::{CRC, RCC}; + // todo: Redo this in the style of the rest of our modules. pub trait CrcExt { diff --git a/src/dac.rs b/src/dac.rs index ff984b0..05613a4 100644 --- a/src/dac.rs +++ b/src/dac.rs @@ -2,10 +2,9 @@ use core::ops::Deref; -use cortex_m::interrupt::free; - #[cfg(not(any(feature = "f3", feature = "f4", feature = "l5", feature = "g4")))] use cortex_m::delay::Delay; +use cortex_m::interrupt::free; use crate::{ pac::{self, RCC}, @@ -20,17 +19,15 @@ cfg_if! { } } +#[cfg(any(feature = "f3", feature = "l4"))] +use crate::dma::DmaInput; +#[cfg(not(any(feature = "f4", feature = "l552")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; #[cfg(feature = "g0")] use crate::pac::DMA as DMA1; #[cfg(not(feature = "g0"))] use crate::pac::DMA1; -#[cfg(not(any(feature = "f4", feature = "l552")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - -#[cfg(any(feature = "f3", feature = "l4"))] -use crate::dma::DmaInput; - #[derive(Clone, Copy)] #[repr(u8)] /// Sets the DAC_MCR register, Mode1 and Mode2 fields. diff --git a/src/dfsdm.rs b/src/dfsdm.rs index 8048d86..8951dca 100644 --- a/src/dfsdm.rs +++ b/src/dfsdm.rs @@ -5,8 +5,8 @@ use core::ops::Deref; +use cfg_if::cfg_if; use cortex_m::interrupt::free; - use num_traits::Float; // Float rounding. use crate::{ @@ -15,8 +15,6 @@ use crate::{ util::rcc_en_reset, }; -use cfg_if::cfg_if; - cfg_if! { if #[cfg(any(feature = "l4", feature = "l5", feature = "h7b3"))] { use crate::pac::dfsdm1 as dfsdm_p; @@ -25,13 +23,11 @@ cfg_if! { } } -use crate::pac::DMA1; - -#[cfg(not(any(feature = "f4", feature = "l552")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - #[cfg(any(feature = "f3", feature = "l4"))] use crate::dma::DmaInput; +#[cfg(not(any(feature = "f4", feature = "l552")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; +use crate::pac::DMA1; #[derive(Clone, Copy)] pub enum Filter { diff --git a/src/dma.rs b/src/dma.rs index 7121070..e409244 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -37,19 +37,15 @@ cfg_if! { } } +// use embedded_dma::{ReadBuffer, WriteBuffer}; +use cfg_if::cfg_if; #[cfg(any(feature = "g0", feature = "g4", feature = "wl"))] use pac::DMAMUX; - // todo: DMAMUX2 support (Not sure if WB has it, but H7 has both). #[cfg(any(feature = "l5", feature = "wb", feature = "h7"))] use pac::DMAMUX1 as DMAMUX; - #[cfg(feature = "h7")] use pac::DMAMUX2; - -// use embedded_dma::{ReadBuffer, WriteBuffer}; - -use cfg_if::cfg_if; use paste::paste; // todo: Several sections of this are only correct for DMA1. diff --git a/src/ethernet.rs b/src/ethernet.rs index fb9e714..8b15979 100644 --- a/src/ethernet.rs +++ b/src/ethernet.rs @@ -7,7 +7,6 @@ use core::ops::Deref; use cortex_m::interrupt::free; - use smoltcp::{ self, phy::{self, Device, DeviceCapabilities, Medium}, diff --git a/src/flash/mod.rs b/src/flash/mod.rs index f767217..9045270 100644 --- a/src/flash/mod.rs +++ b/src/flash/mod.rs @@ -6,10 +6,10 @@ //! Make sure not to write to a page your MCU doesn't have, or that includes your //! program's memory. -use crate::pac::FLASH; - use cfg_if::cfg_if; +use crate::pac::FLASH; + // Note that L5 code is simialr to other families like L4 and G4, but splits many options into // 2 sets; one for secure, one for nonsecure. diff --git a/src/flash/non_trustzone.rs b/src/flash/non_trustzone.rs index 3ee7bc1..5481bc2 100644 --- a/src/flash/non_trustzone.rs +++ b/src/flash/non_trustzone.rs @@ -3,14 +3,12 @@ use core; -use crate::pac::FLASH; - -#[cfg(feature = "h7")] -use crate::pac::flash::BANK; - use cfg_if::cfg_if; use super::{page_to_address, Flash}; +#[cfg(feature = "h7")] +use crate::pac::flash::BANK; +use crate::pac::FLASH; const FLASH_KEY1: u32 = 0x4567_0123; const FLASH_KEY2: u32 = 0xCDEF_89AB; diff --git a/src/flash/trustzone.rs b/src/flash/trustzone.rs index 4c4e9a1..7ebba4e 100644 --- a/src/flash/trustzone.rs +++ b/src/flash/trustzone.rs @@ -4,9 +4,8 @@ use core; use cfg_if::cfg_if; -use crate::pac::FLASH; - use super::{page_to_address, Flash}; +use crate::pac::FLASH; const FLASH_KEY1: u32 = 0x4567_0123; const FLASH_KEY2: u32 = 0xCDEF_89AB; diff --git a/src/gpio.rs b/src/gpio.rs index 7136c54..888fa29 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -10,15 +10,13 @@ use core::convert::Infallible; use cortex_m::interrupt::free; +#[cfg(feature = "embedded_hal")] +use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin}; use crate::pac::{self, EXTI, RCC}; - #[cfg(not(feature = "h7"))] use crate::util::rcc_en_reset; -#[cfg(feature = "embedded_hal")] -use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin}; - // #[cfg(not(any( // // feature = "g0", // feature = "f4", @@ -36,12 +34,12 @@ cfg_if! { } } -#[cfg(not(any(feature = "f4", feature = "l552", feature = "h5")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - use cfg_if::cfg_if; use paste::paste; +#[cfg(not(any(feature = "f4", feature = "l552", feature = "h5")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; + #[derive(Copy, Clone)] #[repr(u8)] /// Values for `GPIOx_MODER`. Sets pin to input, output, and other functionality. diff --git a/src/hsem.rs b/src/hsem.rs index 6acdfab..65660e2 100644 --- a/src/hsem.rs +++ b/src/hsem.rs @@ -1,12 +1,11 @@ //! Hardware semaphore (HSEM) //! Used on STM32WB to synchronize processes running on different cores. -use crate::pac::{self, HSEM, RCC}; - use cortex_m::interrupt::free; - use paste::paste; +use crate::pac::{self, HSEM, RCC}; + #[derive(Clone, Copy)] /// The core that's performing the requested operation. Core 1 is the M4 core, and Core 2 is the M0+ core. pub enum Core { diff --git a/src/i2c.rs b/src/i2c.rs index ec95c7d..b0ed13b 100644 --- a/src/i2c.rs +++ b/src/i2c.rs @@ -5,27 +5,23 @@ use core::ops::Deref; use cortex_m::interrupt::free; - #[cfg(feature = "embedded_hal")] use embedded_hal::blocking::i2c::{Read, Write, WriteRead}; -use crate::{ - clocks::Clocks, - pac::{self, RCC}, - util::RccPeriph, - MAX_ITERS, -}; - -#[cfg(not(any(feature = "l552", feature = "h5")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - #[cfg(any(feature = "f3", feature = "l4"))] use crate::dma::DmaInput; - +#[cfg(not(any(feature = "l552", feature = "h5")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; #[cfg(feature = "g0")] use crate::pac::DMA as DMA1; #[cfg(not(any(feature = "g0", feature = "h5")))] use crate::pac::DMA1; +use crate::{ + clocks::Clocks, + pac::{self, RCC}, + util::RccPeriph, + MAX_ITERS, +}; macro_rules! busy_wait { ($regs:expr, $flag:ident) => { diff --git a/src/i2c_f4.rs b/src/i2c_f4.rs index fab537d..e365ddf 100644 --- a/src/i2c_f4.rs +++ b/src/i2c_f4.rs @@ -8,9 +8,9 @@ use core::ops::Deref; use cortex_m::interrupt::free; - #[cfg(feature = "embedded_hal")] use embedded_hal::blocking::i2c::{Read, Write, WriteRead}; +use paste::paste; use crate::{ clocks::Clocks, @@ -18,8 +18,6 @@ use crate::{ util::rcc_en_reset, }; -use paste::paste; - #[derive(Clone, Copy)] pub enum I2cDevice { One, diff --git a/src/ipcc.rs b/src/ipcc.rs index 2843a95..e41a987 100644 --- a/src/ipcc.rs +++ b/src/ipcc.rs @@ -1,10 +1,10 @@ //! Inter-processor communication controller (IPCC). //! Used on STM32WB for communication between cores. -use crate::pac::{self, IPCC, RCC}; - use cortex_m::interrupt::free; +use crate::pac::{self, IPCC, RCC}; + // todo: C1_1 and C2_1 etc for channels instead of separate core enum? // todo: Consider macros to reduce DRY here, re Core and Channel matching. // todo: Consolidate match arms to reduce DRY match statements for the diff steps diff --git a/src/iwdg.rs b/src/iwdg.rs index 63604d0..a9ea3f9 100644 --- a/src/iwdg.rs +++ b/src/iwdg.rs @@ -2,7 +2,6 @@ #[cfg(not(any(feature = "h735", feature = "h747cm4", feature = "h747cm7")))] use crate::pac::IWDG; - #[cfg(any(feature = "h735", feature = "h747cm4", feature = "h747cm7"))] use crate::pac::IWDG1 as IWDG; diff --git a/src/lib.rs b/src/lib.rs index 3271f0a..c224b49 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -199,198 +199,138 @@ compile_error!("This crate requires an MCU-specifying feature to be enabled. eg // Re-export of the [svd2rust](https://crates.io/crates/svd2rust) auto-generated API for // stm32 peripherals. +// todo: U5 once SVD is out. +use cfg_if::cfg_if; +use cortex_m::{self, delay::Delay}; #[cfg(feature = "f301")] pub use stm32f3::stm32f301 as pac; - #[cfg(feature = "f302")] pub use stm32f3::stm32f302 as pac; - #[cfg(feature = "f303")] pub use stm32f3::stm32f303 as pac; - #[cfg(feature = "f373")] pub use stm32f3::stm32f373 as pac; - #[cfg(feature = "f3x4")] pub use stm32f3::stm32f3x4 as pac; - // F4 PAC #[cfg(feature = "f401")] pub use stm32f4::stm32f401 as pac; - #[cfg(feature = "f405")] pub use stm32f4::stm32f405 as pac; - #[cfg(feature = "f407")] pub use stm32f4::stm32f407 as pac; - #[cfg(feature = "f410")] pub use stm32f4::stm32f410 as pac; - #[cfg(feature = "f411")] pub use stm32f4::stm32f411 as pac; - #[cfg(feature = "f412")] pub use stm32f4::stm32f412 as pac; - #[cfg(feature = "f413")] pub use stm32f4::stm32f413 as pac; - #[cfg(feature = "f427")] pub use stm32f4::stm32f427 as pac; - #[cfg(feature = "f429")] pub use stm32f4::stm32f429 as pac; - #[cfg(feature = "f446")] pub use stm32f4::stm32f446 as pac; - #[cfg(feature = "f469")] pub use stm32f4::stm32f469 as pac; - -// L4 PAC -#[cfg(feature = "l4x1")] -pub use stm32l4::stm32l4x1 as pac; - -#[cfg(feature = "l4x2")] -pub use stm32l4::stm32l4x2 as pac; - -#[cfg(feature = "l412")] -pub use stm32l4::stm32l412 as pac; - -#[cfg(feature = "l4x3")] -pub use stm32l4::stm32l4x3 as pac; - -#[cfg(feature = "l4x5")] -pub use stm32l4::stm32l4x5 as pac; - -#[cfg(feature = "l4x6")] -pub use stm32l4::stm32l4x6 as pac; - -// L5 PAC -#[cfg(feature = "l552")] -pub use stm32l5::stm32l552 as pac; - -#[cfg(feature = "l562")] -pub use stm32l5::stm32l562 as pac; - // todo: Test and make accomodations for recently added G0 variants 50, 51, 61, B0, B1 and C1, in // todo the individual modules. // G0 PAC #[cfg(feature = "g030")] pub use stm32g0::stm32g030 as pac; - #[cfg(feature = "g031")] pub use stm32g0::stm32g031 as pac; - #[cfg(feature = "g041")] pub use stm32g0::stm32g041 as pac; - #[cfg(feature = "g050")] pub use stm32g0::stm32g050 as pac; - #[cfg(feature = "g051")] pub use stm32g0::stm32g051 as pac; - #[cfg(feature = "g061")] pub use stm32g0::stm32g061 as pac; - #[cfg(feature = "g070")] pub use stm32g0::stm32g070 as pac; - #[cfg(feature = "g071")] pub use stm32g0::stm32g071 as pac; - #[cfg(feature = "g081")] pub use stm32g0::stm32g081 as pac; - #[cfg(feature = "g0b0")] pub use stm32g0::stm32g0b0 as pac; - #[cfg(feature = "g0b1")] pub use stm32g0::stm32g0b1 as pac; - #[cfg(feature = "g0c1")] pub use stm32g0::stm32g0c1 as pac; - // G4 PAC #[cfg(feature = "g431")] pub use stm32g4::stm32g431 as pac; - #[cfg(feature = "g441")] pub use stm32g4::stm32g441 as pac; - #[cfg(feature = "g471")] pub use stm32g4::stm32g471 as pac; - #[cfg(feature = "g473")] pub use stm32g4::stm32g473 as pac; - #[cfg(feature = "g474")] pub use stm32g4::stm32g474 as pac; - #[cfg(feature = "g483")] pub use stm32g4::stm32g483 as pac; - #[cfg(feature = "g484")] pub use stm32g4::stm32g484 as pac; - #[cfg(feature = "g491")] pub use stm32g4::stm32g491 as pac; - #[cfg(feature = "g4a1")] pub use stm32g4::stm32g4a1 as pac; - // H5 PAC #[cfg(feature = "h503")] pub use stm32h5::stm32h503 as pac; - #[cfg(feature = "h562")] pub use stm32h5::stm32h562 as pac; - #[cfg(feature = "h563")] pub use stm32h5::stm32h563 as pac; - #[cfg(feature = "h573")] pub use stm32h5::stm32h573 as pac; - // H7 PAC #[cfg(feature = "h735")] pub use stm32h7::stm32h735 as pac; - #[cfg(feature = "h743")] pub use stm32h7::stm32h743 as pac; - #[cfg(feature = "h743v")] pub use stm32h7::stm32h743v as pac; - #[cfg(feature = "h747cm4")] pub use stm32h7::stm32h747cm4 as pac; - #[cfg(feature = "h747cm7")] pub use stm32h7::stm32h747cm7 as pac; - #[cfg(feature = "h753")] pub use stm32h7::stm32h753 as pac; - #[cfg(feature = "h753v")] pub use stm32h7::stm32h753v as pac; - #[cfg(feature = "h7b3")] pub use stm32h7::stm32h7b3 as pac; - +#[cfg(feature = "l412")] +pub use stm32l4::stm32l412 as pac; +// L4 PAC +#[cfg(feature = "l4x1")] +pub use stm32l4::stm32l4x1 as pac; +#[cfg(feature = "l4x2")] +pub use stm32l4::stm32l4x2 as pac; +#[cfg(feature = "l4x3")] +pub use stm32l4::stm32l4x3 as pac; +#[cfg(feature = "l4x5")] +pub use stm32l4::stm32l4x5 as pac; +#[cfg(feature = "l4x6")] +pub use stm32l4::stm32l4x6 as pac; +// L5 PAC +#[cfg(feature = "l552")] +pub use stm32l5::stm32l552 as pac; +#[cfg(feature = "l562")] +pub use stm32l5::stm32l562 as pac; #[cfg(feature = "wb55")] pub use stm32wb::stm32wb55 as pac; - #[cfg(feature = "wle5")] pub use stm32wl::stm32wle5 as pac; -// todo: U5 once SVD is out. - -use cfg_if::cfg_if; -use cortex_m::{self, delay::Delay}; - #[cfg(not(any(feature = "f301", feature = "f302")))] pub mod adc; diff --git a/src/low_power.rs b/src/low_power.rs index 508d678..b908e58 100644 --- a/src/low_power.rs +++ b/src/low_power.rs @@ -1,18 +1,15 @@ //! This module contains code used to place the MCU in low power modes. //! Reference section 5.3.3: `Low power modes` of the L4 Reference Manual. -#[cfg(not(feature = "h7"))] -use crate::pac::PWR; - -#[cfg(any(feature = "l4", feature = "l5"))] -use crate::pac; +use cfg_if::cfg_if; +use cortex_m::{asm::wfi, Peripherals}; #[cfg(any(feature = "l4", feature = "l5"))] use crate::clocks::{Clocks, MsiRange}; - -use cortex_m::{asm::wfi, Peripherals}; - -use cfg_if::cfg_if; +#[cfg(any(feature = "l4", feature = "l5"))] +use crate::pac; +#[cfg(not(feature = "h7"))] +use crate::pac::PWR; // See L4 Reference Manual section 5.3.6. The values correspond to the PWR_CR1 LPMS bits. // todo PWR_CR1, LPMS field. diff --git a/src/rng.rs b/src/rng.rs index 127f17b..d2dbee7 100644 --- a/src/rng.rs +++ b/src/rng.rs @@ -1,5 +1,6 @@ //! Support for the Random Number Generator (RNG) peripheral. +use cfg_if::cfg_if; use cortex_m::interrupt::free; use crate::{ @@ -7,8 +8,6 @@ use crate::{ util::rcc_en_reset, }; -use cfg_if::cfg_if; - /// Represents a RNG peripheral. pub struct Rng { pub regs: RNG, diff --git a/src/rtc.rs b/src/rtc.rs index 615b49c..484d19b 100644 --- a/src/rtc.rs +++ b/src/rtc.rs @@ -4,12 +4,12 @@ //! Uses [Chrono](https://docs.rs/chrono) for dates and times. -use crate::pac::{EXTI, PWR, RCC, RTC}; use core::convert::TryInto; +use cfg_if::cfg_if; use chrono::{Datelike, NaiveDate, NaiveDateTime, NaiveTime, Timelike}; -use cfg_if::cfg_if; +use crate::pac::{EXTI, PWR, RCC, RTC}; // todo: QC use of ICSR vice SR and ISR wherever used in this module! diff --git a/src/sai.rs b/src/sai.rs index 067371b..20080a4 100644 --- a/src/sai.rs +++ b/src/sai.rs @@ -3,17 +3,10 @@ use core::ops::Deref; -use crate::{clocks::Clocks, pac::RCC, util::RccPeriph}; - -#[cfg(not(any(feature = "g4", feature = "h7")))] -use crate::pac::sai1 as sai; - -#[cfg(feature = "g4")] -use crate::pac::sai; - -#[cfg(feature = "h7")] -use crate::pac::sai4 as sai; - +#[cfg(any(feature = "f3", feature = "l4"))] +use crate::dma::DmaInput; +#[cfg(not(any(feature = "f4", feature = "l552")))] +use crate::dma::{self, ChannelCfg, Dma, DmaChannel}; #[cfg(feature = "g0")] use crate::pac::dma as dma_p; #[cfg(any( @@ -25,12 +18,13 @@ use crate::pac::dma as dma_p; feature = "wb" ))] use crate::pac::dma1 as dma_p; - -#[cfg(not(any(feature = "f4", feature = "l552")))] -use crate::dma::{self, ChannelCfg, Dma, DmaChannel}; - -#[cfg(any(feature = "f3", feature = "l4"))] -use crate::dma::DmaInput; +#[cfg(feature = "g4")] +use crate::pac::sai; +#[cfg(not(any(feature = "g4", feature = "h7")))] +use crate::pac::sai1 as sai; +#[cfg(feature = "h7")] +use crate::pac::sai4 as sai; +use crate::{clocks::Clocks, pac::RCC, util::RccPeriph}; #[derive(Clone, Copy)] #[repr(u8)] diff --git a/src/spi.rs b/src/spi.rs index f2ce941..1d50d53 100644 --- a/src/spi.rs +++ b/src/spi.rs @@ -4,6 +4,7 @@ use core::{ops::Deref, ptr}; +use cfg_if::cfg_if; #[cfg(feature = "embedded_hal")] use embedded_hal::spi::FullDuplex; @@ -13,8 +14,6 @@ use crate::{ MAX_ITERS, }; -use cfg_if::cfg_if; - cfg_if! { if #[cfg(all(feature = "g0", not(any(feature = "g0b1", feature = "g0c1"))))] { use crate::pac::dma as dma_p; @@ -25,13 +24,12 @@ cfg_if! { } } -#[cfg(not(any(feature = "f4", feature = "l552")))] -use crate::dma::{self, ChannelCfg, Dma, DmaChannel}; +use defmt::println; #[cfg(any(feature = "f3", feature = "l4"))] use crate::dma::DmaInput; - -use defmt::println; // todo temp +#[cfg(not(any(feature = "f4", feature = "l552")))] +use crate::dma::{self, ChannelCfg, Dma, DmaChannel}; // todo temp /// SPI error #[non_exhaustive] @@ -611,7 +609,11 @@ where } #[cfg(not(any(feature = "h5", feature = "h7")))] - pub fn transfer_type2<'w>(&mut self, write_buf: &'w [u8], read_buf: &'w mut [u8]) -> Result<(), SpiError> { + pub fn transfer_type2<'w>( + &mut self, + write_buf: &'w [u8], + read_buf: &'w mut [u8], + ) -> Result<(), SpiError> { println!("Write buf: {:?}, Read buf: {:?}", write_buf, read_buf); let mut i_read = 0; diff --git a/src/timer.rs b/src/timer.rs index 73722ab..4311e35 100644 --- a/src/timer.rs +++ b/src/timer.rs @@ -5,22 +5,19 @@ // todo: WB and WL should support pwm features +#[cfg(feature = "monotonic")] +use core; use core::{ ops::Deref, sync::atomic::{AtomicU32, Ordering}, }; +use cfg_if::cfg_if; use cortex_m::interrupt::free; - +use paste::paste; #[cfg(feature = "monotonic")] use rtic_monotonic::Monotonic; -#[cfg(feature = "monotonic")] -use core; - -use cfg_if::cfg_if; -use paste::paste; - cfg_if! { if #[cfg(feature = "embedded_hal")] { use embedded_hal::{ @@ -34,8 +31,15 @@ cfg_if! { use num_traits::float::FloatCore; // To round floats. +#[cfg(any(feature = "f3", feature = "l4"))] +use crate::dma::DmaInput; +#[cfg(not(any(feature = "f4", feature = "l552")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; +#[cfg(feature = "g0")] +use crate::pac::DMA as DMA1; +#[cfg(not(feature = "g0"))] +use crate::pac::DMA1; // todo: LPTIM (low-power timers) and HRTIM (high-resolution timers). And Advanced control functionality - use crate::{ clocks::Clocks, instant::Instant, @@ -43,17 +47,6 @@ use crate::{ util::{rcc_en_reset, RccPeriph}, }; -#[cfg(not(any(feature = "f4", feature = "l552")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - -#[cfg(any(feature = "f3", feature = "l4"))] -use crate::dma::DmaInput; - -#[cfg(feature = "g0")] -use crate::pac::DMA as DMA1; -#[cfg(not(feature = "g0"))] -use crate::pac::DMA1; - // This `TICK_OVERFLOW_COUNT` must be incremented in firmware in the timer's update interrupt. pub static TICK_OVERFLOW_COUNT: AtomicU32 = AtomicU32::new(0); diff --git a/src/usart.rs b/src/usart.rs index 563a30f..de34906 100644 --- a/src/usart.rs +++ b/src/usart.rs @@ -7,28 +7,10 @@ // todo: Missing some features (like additional interrupts) on the USARTv3 peripheral . (L5, G etc) -use crate::{ - clocks::Clocks, - pac::{self, RCC}, - util::{BaudPeriph, RccPeriph}, - MAX_ITERS, -}; - use core::ops::Deref; +use cfg_if::cfg_if; use cortex_m::interrupt::free; - -#[cfg(not(any(feature = "f4", feature = "l552", feature = "h5")))] -use crate::dma::{self, ChannelCfg, DmaChannel}; - -#[cfg(any(feature = "f3", feature = "l4"))] -use crate::dma::DmaInput; - -#[cfg(feature = "g0")] -use crate::pac::DMA as DMA1; -#[cfg(not(any(feature = "g0", feature = "h5")))] -use crate::pac::DMA1; - #[cfg(feature = "embedded_hal")] use embedded_hal::{ blocking, @@ -37,7 +19,20 @@ use embedded_hal::{ #[cfg(feature = "embedded_hal")] use nb; -use cfg_if::cfg_if; +#[cfg(any(feature = "f3", feature = "l4"))] +use crate::dma::DmaInput; +#[cfg(not(any(feature = "f4", feature = "l552", feature = "h5")))] +use crate::dma::{self, ChannelCfg, DmaChannel}; +#[cfg(feature = "g0")] +use crate::pac::DMA as DMA1; +#[cfg(not(any(feature = "g0", feature = "h5")))] +use crate::pac::DMA1; +use crate::{ + clocks::Clocks, + pac::{self, RCC}, + util::{BaudPeriph, RccPeriph}, + MAX_ITERS, +}; // todo: Prescaler (USART_PRESC) register on v3 (L5, G, H etc) diff --git a/src/usb.rs b/src/usb.rs index ade72d2..056691b 100644 --- a/src/usb.rs +++ b/src/usb.rs @@ -20,17 +20,13 @@ Strangely, the register modification commands for the l4x5 have OTG in their names */ -use crate::{pac, util::rcc_en_reset}; - -#[cfg(any(feature = "l4", feature = "l5", feature = "g0"))] -use crate::pac::PWR; - -use crate::pac::USB; - +use cfg_if::cfg_if; pub use stm32_usbd::UsbBus; use stm32_usbd::UsbPeripheral; -use cfg_if::cfg_if; +#[cfg(any(feature = "l4", feature = "l5", feature = "g0"))] +use crate::pac::PWR; +use crate::{pac, pac::USB, util::rcc_en_reset}; /// Represents a Universal Serial Bus (USB) peripheral. Functionality is implemented through the /// implemented `stm32_usbd::UsbPeripheral` trait. diff --git a/src/usb_otg.rs b/src/usb_otg.rs index 0ff73fb..320c444 100644 --- a/src/usb_otg.rs +++ b/src/usb_otg.rs @@ -11,15 +11,15 @@ compile_error!("target only supports usbotg_hs feature"); #[cfg(all(not(feature = "h7"), feature = "usbotg_hs"))] compile_error!("target only supports usbotg_fs feature"); +use cfg_if::cfg_if; +pub use synopsys_usb_otg::UsbBus; +use synopsys_usb_otg::UsbPeripheral; + use crate::{ gpio::Pin, pac::{self, PWR, RCC}, }; -use cfg_if::cfg_if; -pub use synopsys_usb_otg::UsbBus; -use synopsys_usb_otg::UsbPeripheral; - cfg_if! { if #[cfg(feature = "usbotg_hs")] { // On older H7s (H743 etc), OTG1 maps to pisn PB14 and PB15. diff --git a/src/util.rs b/src/util.rs index 7b14727..894d809 100644 --- a/src/util.rs +++ b/src/util.rs @@ -3,22 +3,19 @@ #[cfg(feature = "l4")] use core::ops::Deref; -use crate::{ - clocks::Clocks, - pac::{self, rcc::RegisterBlock}, -}; +use cfg_if::cfg_if; +// todo: L5 has a PAC bug on CCR registers past 1. #[cfg(any(feature = "f3", feature = "l4"))] -use crate::pac::DMA1; - +use crate::dma::{self, Dma, DmaChannel, DmaInput}; #[cfg(feature = "l4")] use crate::pac::dma1; - -// todo: L5 has a PAC bug on CCR registers past 1. #[cfg(any(feature = "f3", feature = "l4"))] -use crate::dma::{self, Dma, DmaChannel, DmaInput}; - -use cfg_if::cfg_if; +use crate::pac::DMA1; +use crate::{ + clocks::Clocks, + pac::{self, rcc::RegisterBlock}, +}; #[cfg(not(any( feature = "f401",