From 69c3cb751cda32e7dfff4e213cc123b261647ede Mon Sep 17 00:00:00 2001
From: yufeng <321353225@qq.com>
Date: Wed, 24 Jul 2024 10:18:39 +0800
Subject: [PATCH] feat: add doc and test script

---
 .cargo/config.toml | 8 ++++++++
 src/riscv64/mod.rs | 9 +++++++++
 2 files changed, 17 insertions(+)

diff --git a/.cargo/config.toml b/.cargo/config.toml
index bac0add..921cf19 100644
--- a/.cargo/config.toml
+++ b/.cargo/config.toml
@@ -4,3 +4,11 @@ target = "riscv64gc-unknown-none-elf"
 # target = 'aarch64-unknown-none-softfloat'
 # target = 'x86_64-unknown-none'
 # target = 'loongarch64-unknown-none'
+
+[target.'cfg(target_os = "none")']
+runner = "./test.sh"
+rustflags = [
+    "-Clink-arg=-Texample/linker/linker-riscv64.ld",
+    "-Cforce-frame-pointers=yes",
+    '--cfg=board="qemu"',
+]
diff --git a/src/riscv64/mod.rs b/src/riscv64/mod.rs
index 7f01a4a..a412bee 100644
--- a/src/riscv64/mod.rs
+++ b/src/riscv64/mod.rs
@@ -201,6 +201,8 @@ impl MultiCore {
     }
 }
 
+/// PolyHAL defined percpu reserved fields.
+/// Just used in the polyHAL and context switch.
 #[repr(C)]
 pub(crate) struct PerCPUReserved {
     pub user_rsp: usize,
@@ -208,6 +210,13 @@ pub(crate) struct PerCPUReserved {
     pub user_context: usize,
 }
 
+/// Get the offset of the specified percpu field.
+/// 
+/// PerCPU Arrange is that.
+/// 
+/// IN x86_64. The Reserved fields was used in manually.
+/// IN other architectures, the reserved fields was defined 
+/// negative offset of the percpu pointer.
 pub macro PerCPUReservedOffset($field: ident) {
     core::mem::offset_of!(PerCPUReserved, $field) as isize
         - core::mem::size_of::<PerCPUReserved>() as isize